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202 lines
6.0 KiB
C
202 lines
6.0 KiB
C
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief
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*
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* This file contains configuration APIs doing MSPI timing tuning by MSPI DQS
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
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#include "mspi_timing_tuning_configs.h"
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#include "hal/mspi_timing_tuning_ll.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
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#define IS_DDR 1
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#define IS_SDR (!IS_DDR)
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/**
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* Delayline
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*/
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typedef struct {
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uint8_t data_delayline;
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uint8_t dqs_delayline;
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} __attribute__((packed)) delayline_config_t;
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/**
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* MSPI timing tuning configurations
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*/
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typedef struct {
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mspi_ll_dqs_phase_t phase[MSPI_LL_DQS_PHASE_MAX];
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delayline_config_t delayline_table[MSPI_TIMING_CONFIG_NUM_MAX];
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union {
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uint32_t available_config_num;
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uint32_t available_phase_num;
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};
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} mspi_timing_config_t;
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/*-------------------------------------------------------------------------------------------------
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* Timing Required APIs
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*-------------------------------------------------------------------------------------------------*/
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/**
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* @brief Init MSPI for PSRAM timing tuning
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*
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* @param[in] psram_freq_mhz PSRAM frequency in MHz
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*/
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void mspi_timing_psram_init(uint32_t psram_freq_mhz);
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/**
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* @brief Prepare reference data buffer
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*/
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void mspi_timing_config_psram_prepare_reference_data(uint8_t *buf, uint32_t len);
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/**
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* @brief Configure PSRAM to write data via MSPI3
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*
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* @param[in] buf buffer
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* @param[in] addr address
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* @param[in] len length
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*/
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void mspi_timing_config_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len);
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/**
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* @brief Configure PSRAM to read data via MSPI3
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*
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* @param[out] buf buffer
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* @param[in] addr address
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* @param[in] len length
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*/
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void mspi_timing_config_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len);
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/**
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* @brief Get PSRAM tuning configurations for phase
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*
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* @param[out] config Pointer to PSRAM tuning configurations
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*/
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void mspi_timing_get_psram_tuning_phases(mspi_timing_config_t *configs);
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/**
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* @brief Tune PSRAM timing registers for MSPI3 accessing PSRAM
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*
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* @param[in] configs Timing configs
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* @param[in] id Config ID
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*/
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void mspi_timing_config_psram_set_tuning_phase(const void *configs, uint8_t id);
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/**
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* @brief Select PSRAM best tuning configuration
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*
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* @param[in] configs Timing tuning configuration table
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* @param[in] consecutive_length Length of the consecutive successful sample results
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* @param[in] end End of the consecutive successful sample results
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* @param[in] reference_data Reference data
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* @param[in] is_ddr DDR or SDR
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*
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* @return Best config ID
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*/
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uint32_t mspi_timing_psram_select_best_tuning_phase(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr);
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/**
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* @brief Set best PSRAM tuning configs.
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* After this, calling `mspi_timing_enter_high_speed_mode` will set these configs correctly
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*
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* @param[in] configs Timing tuning configs
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* @param[in] best_id Best config ID
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*/
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void mspi_timing_psram_set_best_tuning_phase(const void *configs, uint8_t best_id);
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/**
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* @brief Get PSRAM tuning configurations for delayline
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*
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* @param[out] config Pointer to PSRAM tuning configurations
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*/
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void mspi_timing_get_psram_tuning_delaylines(mspi_timing_config_t *configs);
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/**
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* @brief Tune PSRAM timing registers for MSPI3 accessing PSRAM
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*
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* @param[in] configs Timing configs
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* @param[in] id Config ID
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*/
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void mspi_timing_config_psram_set_tuning_delayline(const void *configs, uint8_t id);
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/**
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* @brief Select PSRAM best tuning configuration
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*
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* @param[in] configs Timing tuning configuration table
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* @param[in] consecutive_length Length of the consecutive successful sample results
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* @param[in] end End of the consecutive successful sample results
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* @param[in] reference_data Reference data
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* @param[in] is_ddr DDR or SDR
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*
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* @return Best config ID
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*/
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uint32_t mspi_timing_psram_select_best_tuning_delayline(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr);
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/**
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* @brief Set best PSRAM tuning configs.
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* After this, calling `mspi_timing_enter_high_speed_mode` will set these configs correctly
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*
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* @param[in] configs Timing tuning configs
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* @param[in] best_id Best config ID
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*/
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void mspi_timing_psram_set_best_tuning_delayline(const void *configs, uint8_t best_id);
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/*-------------------------------------------------------------------------------------------------
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* General Timing APIs
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*-------------------------------------------------------------------------------------------------*/
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/**
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* @brief Set PSRAM timing tuning settings
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*
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* This is used when the system is going to high speed mode / MSPI needs to be run in high speed
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*
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* @param[in] control_both_mspi Control MSPI3 as well
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*/
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void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi);
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/**
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* @brief Clear PSRAM timing tuning settings
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*
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* This is used when the system is going into low speed mode / MSPI doesn't need to be run in high speed
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*
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* @param[in] control_both_mspi Control MSPI3 as well
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*/
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void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi);
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/**
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* @brief Set Flash timing tuning settings
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*
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* This is used when the system is going to high speed mode / MSPI needs to be run in high speed
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*
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* @param[in] control_both_mspi Control MSPI1 as well
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*/
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void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi);
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/**
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* @brief Clear Flash timing tuning settings
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*
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* This is used when the system is going into low speed mode / MSPI doesn't need to be run in high speed
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*
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* @param[in] control_both_mspi Control MSPI1 as well
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*/
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void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi);
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#endif //#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
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#ifdef __cplusplus
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}
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#endif
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