mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
297 lines
11 KiB
C
297 lines
11 KiB
C
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/*
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "soc/soc_caps.h"
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#include "esp_eth_com.h"
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#include "esp_eth_mac.h"
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_ETH_USE_ESP32_EMAC
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/**
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* @brief RMII Clock Mode Options
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*
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*/
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typedef enum {
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/**
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* @brief Default values configured using Kconfig are going to be used when "Default" selected.
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*
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* @warning Deprecated option. Clock configuration using Kconfig is limitedly supported only for ESP32 SoC via @c ETH_ESP32_EMAC_DEFAULT_CONFIG
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* and is going to be reevaluated in the next major release.
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* Clock mode and clock GPIO number is supposed to be defined in `EMAC specific configuration` structure from user's code.
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*
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*/
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EMAC_CLK_DEFAULT __attribute__((deprecated)), // IDF-9724
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/**
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* @brief Input RMII Clock from external. EMAC Clock GPIO number needs to be configured when this option is selected.
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*
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* @note MAC will get RMII clock from outside. Note that ESP32 only supports GPIO0 to input the RMII clock.
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*
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*/
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EMAC_CLK_EXT_IN,
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/**
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* @brief Output RMII Clock from internal (A/M)PLL Clock. EMAC Clock GPIO number needs to be configured when this option is selected.
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*
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*/
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EMAC_CLK_OUT
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} emac_rmii_clock_mode_t;
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#if CONFIG_IDF_TARGET_ESP32
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/**
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* @brief RMII Clock GPIO number Options for ESP32
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*
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*/
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typedef enum {
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/**
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* @brief MAC will get RMII clock from outside at this GPIO.
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*
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* @note ESP32 only supports GPIO0 to input the RMII clock.
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*
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*/
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EMAC_CLK_IN_GPIO = 0,
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/**
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* @brief Output RMII Clock from internal APLL Clock available at GPIO0
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*
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* @note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock.
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* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip.
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* You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice.
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* If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.
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*
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*/
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EMAC_APPL_CLK_OUT_GPIO = 0,
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/**
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* @brief Output RMII Clock from internal APLL Clock available at GPIO16
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*
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*/
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EMAC_CLK_OUT_GPIO = 16,
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/**
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* @brief Inverted Output RMII Clock from internal APLL Clock available at GPIO17
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*
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*/
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EMAC_CLK_OUT_180_GPIO = 17
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} emac_rmii_clock_gpio_t;
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#else
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/**
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* @brief RMII Clock GPIO number
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*
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*/
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typedef int emac_rmii_clock_gpio_t;
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#endif // CONFIG_IDF_TARGET_ESP32
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/**
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* @brief Ethernet MAC Clock Configuration
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*
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*/
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typedef union {
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struct {
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// MII interface is not fully implemented...
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// Reserved for GPIO number, clock source, etc. in MII mode
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} mii; /*!< EMAC MII Clock Configuration */
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struct {
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emac_rmii_clock_mode_t clock_mode; /*!< RMII Clock Mode Configuration */
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emac_rmii_clock_gpio_t clock_gpio; /*!< RMII Clock GPIO Configuration */
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} rmii; /*!< EMAC RMII Clock Configuration */
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} eth_mac_clock_config_t;
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/**
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* @brief EMAC SMI GPIO configuration
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*/
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typedef struct {
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int mdc_num; /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
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int mdio_num; /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
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} emac_esp_smi_gpio_config_t;
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/**
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* @brief EMAC MII data interface GPIO configuration
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*/
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typedef struct {
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int tx_clk_num; /*!< TX_CLK GPIO number */
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int tx_en_num; /*!< TX_EN GPIO number */
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int txd0_num; /*!< TXD0 GPIO number */
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int txd1_num; /*!< TXD1 GPIO number */
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int txd2_num; /*!< TXD2 GPIO number */
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int txd3_num; /*!< TXD3 GPIO number */
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int rx_clk_num; /*!< RX_CLK GPIO number */
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int rx_dv_num; /*!< RX_DV GPIO number */
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int rxd0_num; /*!< RXD0 GPIO number */
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int rxd1_num; /*!< RXD1 GPIO number */
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int rxd2_num; /*!< RXD2 GPIO number */
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int rxd3_num; /*!< RXD3 GPIO number */
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int col_in_num; /*!< COL_IN GPIO number */
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int crs_in_num; /*!< CRS_IN GPIO number */
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int tx_er_num; /*!< TX_ER GPIO number */
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int rx_er_num; /*!< RX_ER GPIO number */
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} eth_mac_mii_gpio_config_t;
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/**
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* @brief EMAC RMII data interface GPIO configuration
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*/
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typedef struct {
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int tx_en_num; /*!< TX_EN GPIO number */
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int txd0_num; /*!< TXD0 GPIO number */
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int txd1_num; /*!< TXD1 GPIO number */
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int crs_dv_num; /*!< CRS_DV GPIO number */
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int rxd0_num; /*!< RXD0 GPIO number */
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int rxd1_num; /*!< RXD1 GPIO number */
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} eth_mac_rmii_gpio_config_t;
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#if SOC_EMAC_USE_MULTI_IO_MUX || SOC_EMAC_MII_USE_GPIO_MATRIX
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/**
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* @brief Ethernet MAC MII/RMII data plane GPIO configuration
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*
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*/
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typedef union {
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eth_mac_mii_gpio_config_t mii; /*!< EMAC MII Data GPIO Configuration */
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eth_mac_rmii_gpio_config_t rmii; /*!< EMAC RMII Data GPIO Configuration */
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} eth_mac_dataif_gpio_config_t;
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#endif // SOC_EMAC_USE_MULTI_IO_MUX
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/**
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* @brief EMAC specific configuration
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*
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*/
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typedef struct {
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union {
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emac_esp_smi_gpio_config_t smi_gpio; /*!< SMI GPIO numbers */
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struct {
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int smi_mdc_gpio_num __attribute__((deprecated("Please use smi_gpio instead"))); /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
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int smi_mdio_gpio_num __attribute__((deprecated("Please use smi_gpio instead"))); /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
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};
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};
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eth_data_interface_t interface; /*!< EMAC Data interface to PHY (MII/RMII) */
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eth_mac_clock_config_t clock_config; /*!< EMAC Interface clock configuration */
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eth_mac_dma_burst_len_t dma_burst_len; /*!< EMAC DMA burst length for both Tx and Rx */
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int intr_priority; /*!< EMAC interrupt priority, if set to 0 or a negative value, the driver will try to allocate an interrupt with a default priority */
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#if SOC_EMAC_USE_MULTI_IO_MUX || SOC_EMAC_MII_USE_GPIO_MATRIX
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eth_mac_dataif_gpio_config_t emac_dataif_gpio; /*!< EMAC MII/RMII data plane GPIO configuration */
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#endif // SOC_EMAC_USE_MULTI_IO_MUX
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#if !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
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eth_mac_clock_config_t clock_config_out_in; /*!< EMAC input clock configuration for internally generated output clock (when output clock is looped back externally) */
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#endif //SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
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} eth_esp32_emac_config_t;
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/**
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* @brief List of ESP EMAC specific commands for ioctl API
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*
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*/
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typedef enum {
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ETH_MAC_ESP_CMD_SET_TDES0_CFG_BITS = ETH_CMD_CUSTOM_MAC_CMDS_OFFSET, /*!< Set Transmit Descriptor Word 0 control bit mask (debug option)*/
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ETH_MAC_ESP_CMD_CLEAR_TDES0_CFG_BITS, /*!< Clear Transmit Descriptor Word 0 control bit mask (debug option)*/
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ETH_MAC_ESP_CMD_PTP_ENABLE, /*!< Enable IEEE1588 Time stamping */
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} eth_mac_esp_io_cmd_t;
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/**
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* @brief Default ESP32's EMAC specific configuration
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*
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*/
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_ETH_RMII_CLK_INPUT // IDF-9724
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#define DEFAULT_RMII_CLK_MODE EMAC_CLK_EXT_IN
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#if CONFIG_ETH_RMII_CLK_IN_GPIO == 0
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#define DEFAULT_RMII_CLK_GPIO CONFIG_ETH_RMII_CLK_IN_GPIO
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#else
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#error "ESP32 EMAC only support input RMII clock to GPIO0"
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#endif // CONFIG_ETH_RMII_CLK_IN_GPIO == 0
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#elif CONFIG_ETH_RMII_CLK_OUTPUT
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#define DEFAULT_RMII_CLK_MODE EMAC_CLK_OUT
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#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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#define DEFAULT_RMII_CLK_GPIO EMAC_APPL_CLK_OUT_GPIO
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#else
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#define DEFAULT_RMII_CLK_GPIO CONFIG_ETH_RMII_CLK_OUT_GPIO
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#endif // CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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#else
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#error "Unsupported RMII clock mode"
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#endif // CONFIG_ETH_RMII_CLK_INPUT
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#define ETH_ESP32_EMAC_DEFAULT_CONFIG() \
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{ \
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.smi_gpio = \
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{ \
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.mdc_num = 23, \
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.mdio_num = 18 \
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}, \
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.interface = EMAC_DATA_INTERFACE_RMII, \
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.clock_config = \
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{ \
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.rmii = \
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{ \
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.clock_mode = DEFAULT_RMII_CLK_MODE, \
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.clock_gpio = DEFAULT_RMII_CLK_GPIO \
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} \
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}, \
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.dma_burst_len = ETH_DMA_BURST_LEN_32, \
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.intr_priority = 0, \
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}
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#elif CONFIG_IDF_TARGET_ESP32P4
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#define ETH_ESP32_EMAC_DEFAULT_CONFIG() \
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{ \
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.smi_gpio = \
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{ \
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.mdc_num = 31, \
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.mdio_num = 27 \
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}, \
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.interface = EMAC_DATA_INTERFACE_RMII, \
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.clock_config = \
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{ \
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.rmii = \
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{ \
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.clock_mode = EMAC_CLK_EXT_IN, \
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.clock_gpio = 50 \
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} \
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}, \
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.clock_config_out_in = \
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{ \
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.rmii = \
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{ \
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.clock_mode = EMAC_CLK_EXT_IN, \
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.clock_gpio = -1 \
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} \
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}, \
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.dma_burst_len = ETH_DMA_BURST_LEN_32, \
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.intr_priority = 0, \
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.emac_dataif_gpio = \
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{ \
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.rmii = \
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{ \
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.tx_en_num = 49, \
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.txd0_num = 34, \
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.txd1_num = 35, \
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.crs_dv_num = 28, \
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.rxd0_num = 29, \
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.rxd1_num = 30 \
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} \
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}, \
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}
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#endif // CONFIG_IDF_TARGET_ESP32P4
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/**
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* @brief Create ESP32 Ethernet MAC instance
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*
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* @param esp32_config: EMAC specific configuration
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* @param config: Ethernet MAC configuration
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*
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* @return
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* - instance: create MAC instance successfully
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* - NULL: create MAC instance failed because some error occurred
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*/
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esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config, const eth_mac_config_t *config);
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#endif // CONFIG_ETH_USE_ESP32_EMAC
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#ifdef __cplusplus
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}
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#endif
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