esp-idf/components/riscv/CMakeLists.txt

idf_build_get_property(target IDF_TARGET)
idf_build_get_property(arch IDF_TARGET_ARCH)

if(NOT "${arch}" STREQUAL "riscv")
    return()
endif()


if(BOOTLOADER_BUILD)
    set(priv_requires soc)
else()
    set(priv_requires soc)
    set(srcs
        "instruction_decode.c"
        "interrupt.c"
        "vectors.S")

    if(CONFIG_SOC_INT_CLIC_SUPPORTED)
        list(APPEND srcs "vectors_clic.S")
    else()
        list(APPEND srcs "vectors_intc.S")
    endif()
endif()

idf_component_register(SRCS "${srcs}"
                       LDFRAGMENTS linker.lf
                       INCLUDE_DIRS "include"
                       PRIV_REQUIRES ${priv_requires})
riscv: Add new arch-level component Changes come from internal branch commit a6723fc 2020-11-05 23:03:03 -05:00			`idf_build_get_property(target IDF_TARGET)`
build-system: add property for architecture (riscv/xtensa) riscv/xtensa is now a common component. 2022-05-17 03:13:30 -04:00			`idf_build_get_property(arch IDF_TARGET_ARCH)`
xtensa: simplify build script 2021-01-22 10:06:37 -05:00
build-system: add property for architecture (riscv/xtensa) riscv/xtensa is now a common component. 2022-05-17 03:13:30 -04:00			`if(NOT "${arch}" STREQUAL "riscv")`
riscv: Add new arch-level component Changes come from internal branch commit a6723fc 2020-11-05 23:03:03 -05:00			`return()`
			`endif()`
xtensa: simplify build script 2021-01-22 10:06:37 -05:00
build-system: add property for architecture (riscv/xtensa) riscv/xtensa is now a common component. 2022-05-17 03:13:30 -04:00
riscv: Add new arch-level component Changes come from internal branch commit a6723fc 2020-11-05 23:03:03 -05:00			`if(BOOTLOADER_BUILD)`
			`set(priv_requires soc)`
			`else()`
G0: RISC-V targets have now an independent G0 layer G0 doesn't depend on any G1+ layer for RISC-V based targets 2022-04-26 23:37:08 -04:00			`set(priv_requires soc)`
riscv: Add new arch-level component Changes come from internal branch commit a6723fc 2020-11-05 23:03:03 -05:00			`set(srcs`
interrupt: filter out reserved int number by decoding risc-v JAL instruction 2020-12-30 00:27:00 -05:00			`"instruction_decode.c"`
			`"interrupt.c"`
riscv: Add new arch-level component Changes come from internal branch commit a6723fc 2020-11-05 23:03:03 -05:00			`"vectors.S")`
fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-14 03:44:24 -04:00
			`if(CONFIG_SOC_INT_CLIC_SUPPORTED)`
			`list(APPEND srcs "vectors_clic.S")`
			`else()`
			`list(APPEND srcs "vectors_intc.S")`
			`endif()`
riscv: Add new arch-level component Changes come from internal branch commit a6723fc 2020-11-05 23:03:03 -05:00			`endif()`

			`idf_component_register(SRCS "${srcs}"`
			`LDFRAGMENTS linker.lf`
			`INCLUDE_DIRS "include"`
			`PRIV_REQUIRES ${priv_requires})`