2019-01-08 05:29:25 -05:00
|
|
|
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
|
|
|
//
|
|
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
|
|
// you may not use this file except in compliance with the License.
|
|
|
|
// You may obtain a copy of the License at
|
|
|
|
//
|
|
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
//
|
|
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
|
|
// See the License for the specific language governing permissions and
|
|
|
|
// limitations under the License.
|
|
|
|
|
2020-07-26 15:13:07 -04:00
|
|
|
// HAL for SPI Flash (non-IRAM part)
|
|
|
|
// The IRAM part is in spi_flash_hal_iram.c, spi_flash_hal_gpspi.c, spi_flash_hal_common.inc.
|
|
|
|
|
2019-01-08 05:29:25 -05:00
|
|
|
#include <stdlib.h>
|
|
|
|
#include "hal/spi_flash_hal.h"
|
|
|
|
#include "string.h"
|
2020-09-09 22:37:58 -04:00
|
|
|
#include "soc/soc_caps.h"
|
2019-01-08 05:29:25 -05:00
|
|
|
#include "hal/hal_defs.h"
|
|
|
|
|
|
|
|
#define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
|
|
|
|
|
|
|
|
static const char TAG[] = "FLASH_HAL";
|
|
|
|
|
|
|
|
typedef struct {
|
2020-10-22 00:27:40 -04:00
|
|
|
int div;
|
2019-01-08 05:29:25 -05:00
|
|
|
spi_flash_ll_clock_reg_t clock_reg_val;
|
|
|
|
} spi_flash_hal_clock_config_t;
|
|
|
|
|
|
|
|
|
2020-10-22 00:27:40 -04:00
|
|
|
|
|
|
|
|
2019-01-08 05:29:25 -05:00
|
|
|
static const spi_flash_hal_clock_config_t spi_flash_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
|
2020-10-22 00:27:40 -04:00
|
|
|
{16, SPI_FLASH_LL_CLKREG_VAL_5MHZ},
|
|
|
|
{8, SPI_FLASH_LL_CLKREG_VAL_10MHZ},
|
|
|
|
{4, SPI_FLASH_LL_CLKREG_VAL_20MHZ},
|
|
|
|
{3, SPI_FLASH_LL_CLKREG_VAL_26MHZ},
|
|
|
|
{2, SPI_FLASH_LL_CLKREG_VAL_40MHZ},
|
|
|
|
{1, SPI_FLASH_LL_CLKREG_VAL_80MHZ},
|
2019-01-08 05:29:25 -05:00
|
|
|
};
|
|
|
|
|
2020-11-26 00:06:21 -05:00
|
|
|
#if !CONFIG_IDF_TARGET_ESP32
|
2019-11-27 20:20:00 -05:00
|
|
|
static const spi_flash_hal_clock_config_t spi_flash_gpspi_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
|
2020-10-22 00:27:40 -04:00
|
|
|
{16, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_5MHZ}},
|
|
|
|
{8, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_10MHZ}},
|
|
|
|
{4, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_20MHZ}},
|
|
|
|
{3, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_26MHZ}},
|
|
|
|
{2, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_40MHZ}},
|
|
|
|
{1, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_80MHZ}},
|
2019-11-27 20:20:00 -05:00
|
|
|
};
|
2020-10-22 00:27:40 -04:00
|
|
|
#else
|
|
|
|
#define spi_flash_gpspi_clk_cfg_reg spi_flash_clk_cfg_reg
|
2019-11-27 20:20:00 -05:00
|
|
|
#endif
|
|
|
|
|
2019-01-08 05:29:25 -05:00
|
|
|
static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk)
|
|
|
|
{
|
|
|
|
const int apbclk_kHz = APB_CLK_FREQ / 1000;
|
|
|
|
//calculate how many apb clocks a period has
|
|
|
|
const int apbclk_n = APB_CLK_FREQ / eff_clk;
|
2019-11-27 20:20:00 -05:00
|
|
|
const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0;
|
2019-01-08 05:29:25 -05:00
|
|
|
|
|
|
|
//calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off.
|
|
|
|
int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000;
|
|
|
|
if (apb_period_n < 0) {
|
|
|
|
apb_period_n = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return apb_period_n / apbclk_n;
|
|
|
|
}
|
|
|
|
|
2020-05-07 02:46:41 -04:00
|
|
|
esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg)
|
2019-01-08 05:29:25 -05:00
|
|
|
{
|
2020-08-10 23:57:33 -04:00
|
|
|
if (!esp_ptr_internal(data_out) && cfg->host_id == SPI1_HOST) {
|
2019-01-08 05:29:25 -05:00
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2020-04-07 10:58:26 -04:00
|
|
|
if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2019-11-27 20:20:00 -05:00
|
|
|
|
2020-10-22 00:27:40 -04:00
|
|
|
bool gpspi = (cfg->host_id > SPI_HOST);
|
|
|
|
const spi_flash_hal_clock_config_t *clock_cfg = gpspi? &spi_flash_gpspi_clk_cfg_reg[cfg->speed]: &spi_flash_clk_cfg_reg[cfg->speed];
|
2019-11-27 20:20:00 -05:00
|
|
|
|
2020-05-07 02:46:41 -04:00
|
|
|
*data_out = (spi_flash_hal_context_t) {
|
|
|
|
.inst = data_out->inst, // Keeps the function pointer table
|
2019-01-08 05:29:25 -05:00
|
|
|
.spi = spi_flash_ll_get_hw(cfg->host_id),
|
|
|
|
.cs_num = cfg->cs_num,
|
2020-10-22 00:27:40 -04:00
|
|
|
.extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, APB_CLK_FREQ/clock_cfg->div),
|
|
|
|
.clock_conf = clock_cfg->clock_reg_val,
|
2020-07-26 15:13:07 -04:00
|
|
|
.cs_hold = cfg->cs_hold,
|
2019-01-08 05:29:25 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
ESP_EARLY_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
2019-11-27 20:20:00 -05:00
|
|
|
|
2020-05-07 02:46:41 -04:00
|
|
|
bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p)
|
2019-11-27 20:20:00 -05:00
|
|
|
{
|
2020-05-07 02:46:41 -04:00
|
|
|
bool direct_write = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI_HOST)
|
2019-11-27 20:20:00 -05:00
|
|
|
|| esp_ptr_in_dram(p) );
|
|
|
|
return direct_write;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-05-07 02:46:41 -04:00
|
|
|
bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
|
2019-11-27 20:20:00 -05:00
|
|
|
{
|
|
|
|
//currently the host doesn't support to read through dma, no word-aligned requirements
|
2020-05-07 02:46:41 -04:00
|
|
|
bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI_HOST)
|
2019-11-27 20:20:00 -05:00
|
|
|
|| esp_ptr_in_dram(p) );
|
|
|
|
return direct_read;
|
|
|
|
}
|