2021-02-07 02:03:51 -05:00
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set(INCLUDE_FILES "include" . include PUBLIC soc)
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if(CONFIG_IDF_TARGET_ARCH_RISCV)
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list(APPEND INCLUDE_FILES "include/riscv")
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endif()
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2021-11-23 07:11:33 -05:00
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target_include_directories(${COMPONENT_LIB} PRIVATE ${INCLUDE_FILES} include/private)
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2020-02-02 10:23:16 -05:00
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2023-01-03 05:58:29 -05:00
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set(srcs "cpu_start.c" "panic_handler.c" "esp_system_chip.c")
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2024-05-21 04:45:58 -04:00
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if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
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list(APPEND srcs "image_process.c")
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endif()
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2023-01-03 05:58:29 -05:00
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if(CONFIG_SOC_BOD_SUPPORTED)
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list(APPEND srcs "brownout.c")
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endif()
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2022-11-03 11:59:19 -04:00
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2022-01-18 14:50:33 -05:00
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if(CONFIG_ESP_CONSOLE_USB_CDC)
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list(APPEND srcs "usb_console.c")
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endif()
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2023-08-29 03:55:21 -04:00
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if(CONFIG_ESP_IPC_ISR_ENABLE)
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2023-09-06 07:33:39 -04:00
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list(APPEND srcs "esp_ipc_isr.c")
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if(CONFIG_IDF_TARGET_ARCH_XTENSA)
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list(APPEND srcs "arch/xtensa/esp_ipc_isr_port.c"
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"arch/xtensa/esp_ipc_isr_handler.S"
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"arch/xtensa/esp_ipc_isr_routines.S")
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elseif(CONFIG_IDF_TARGET_ARCH_RISCV)
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list(APPEND srcs "arch/riscv/esp_ipc_isr_port.c"
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"arch/riscv/esp_ipc_isr_handler.S"
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"arch/riscv/esp_ipc_isr_routines.c")
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endif()
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2023-08-29 03:55:21 -04:00
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endif()
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if(CONFIG_IDF_TARGET_ARCH_XTENSA)
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list(APPEND srcs "arch/xtensa/panic_arch.c"
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"arch/xtensa/panic_handler_asm.S"
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"arch/xtensa/expression_with_stack.c"
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"arch/xtensa/expression_with_stack_asm.S"
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"arch/xtensa/debug_helpers.c"
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"arch/xtensa/debug_helpers_asm.S"
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"arch/xtensa/debug_stubs.c"
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"arch/xtensa/trax.c")
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elseif(CONFIG_IDF_TARGET_ARCH_RISCV)
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|
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list(APPEND srcs "arch/riscv/expression_with_stack.c"
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|
|
"arch/riscv/panic_arch.c"
|
2023-08-31 00:19:49 -04:00
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|
|
"arch/riscv/debug_helpers.c"
|
2023-08-29 03:55:21 -04:00
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|
|
"arch/riscv/debug_stubs.c")
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|
|
endif()
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|
2020-02-02 10:23:16 -05:00
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add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})
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|
|
target_sources(${COMPONENT_LIB} PRIVATE ${srcs})
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|
|
idf_build_get_property(target IDF_TARGET)
|
2020-10-08 01:18:16 -04:00
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|
|
add_subdirectory(soc/${target})
|