2018-10-19 09:51:27 -04:00
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/* Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _MB_IFACE_COMMON_H
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#define _MB_IFACE_COMMON_H
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#include "driver/uart.h" // for UART types
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2020-04-17 05:56:50 -04:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2019-04-26 12:47:21 -04:00
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#define MB_CONTROLLER_STACK_SIZE (CONFIG_FMB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller
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2020-07-21 12:34:04 -04:00
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#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_PORT_TASK_PRIO - 1) // priority of MB controller task
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2018-10-19 09:51:27 -04:00
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// Default port defines
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#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus
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#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined
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2019-06-13 23:01:30 -04:00
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#define MB_UART_PORT (UART_NUM_MAX - 1) // Default UART port number
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2018-10-19 09:51:27 -04:00
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#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info
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#define MB_PARITY_NONE (UART_PARITY_DISABLE)
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// The Macros below handle the endianness while transfer N byte data into buffer
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#define _XFER_4_RD(dst, src) { \
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*(uint8_t *)(dst)++ = *(uint8_t*)(src + 1); \
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*(uint8_t *)(dst)++ = *(uint8_t*)(src + 0); \
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*(uint8_t *)(dst)++ = *(uint8_t*)(src + 3); \
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*(uint8_t *)(dst)++ = *(uint8_t*)(src + 2); \
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(src) += 4; \
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}
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#define _XFER_2_RD(dst, src) { \
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*(uint8_t *)(dst)++ = *(uint8_t *)(src + 1); \
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*(uint8_t *)(dst)++ = *(uint8_t *)(src + 0); \
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(src) += 2; \
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}
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#define _XFER_4_WR(dst, src) { \
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*(uint8_t *)(dst + 1) = *(uint8_t *)(src)++; \
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*(uint8_t *)(dst + 0) = *(uint8_t *)(src)++; \
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*(uint8_t *)(dst + 3) = *(uint8_t *)(src)++; \
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*(uint8_t *)(dst + 2) = *(uint8_t *)(src)++ ; \
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}
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#define _XFER_2_WR(dst, src) { \
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*(uint8_t *)(dst + 1) = *(uint8_t *)(src)++; \
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*(uint8_t *)(dst + 0) = *(uint8_t *)(src)++; \
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}
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/**
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* @brief Types of actual Modbus implementation
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*/
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typedef enum
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{
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MB_PORT_SERIAL_MASTER = 0x00, /*!< Modbus port type serial master. */
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MB_PORT_SERIAL_SLAVE, /*!< Modbus port type serial slave. */
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MB_PORT_TCP_MASTER, /*!< Modbus port type TCP master. */
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2020-07-21 12:34:04 -04:00
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MB_PORT_TCP_SLAVE, /*!< Modbus port type TCP slave. */
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MB_PORT_COUNT, /*!< Modbus port count. */
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MB_PORT_INACTIVE = 0xFF
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2018-10-19 09:51:27 -04:00
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} mb_port_type_t;
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/**
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* @brief Event group for parameters notification
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*/
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typedef enum
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{
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MB_EVENT_NO_EVENTS = 0x00,
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MB_EVENT_HOLDING_REG_WR = BIT0, /*!< Modbus Event Write Holding registers. */
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MB_EVENT_HOLDING_REG_RD = BIT1, /*!< Modbus Event Read Holding registers. */
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MB_EVENT_INPUT_REG_RD = BIT3, /*!< Modbus Event Read Input registers. */
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MB_EVENT_COILS_WR = BIT4, /*!< Modbus Event Write Coils. */
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MB_EVENT_COILS_RD = BIT5, /*!< Modbus Event Read Coils. */
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MB_EVENT_DISCRETE_RD = BIT6, /*!< Modbus Event Read Discrete bits. */
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MB_EVENT_STACK_STARTED = BIT7 /*!< Modbus Event Stack started */
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} mb_event_group_t;
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/**
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* @brief Type of Modbus parameter
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*/
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typedef enum {
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MB_PARAM_HOLDING = 0x00, /*!< Modbus Holding register. */
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MB_PARAM_INPUT, /*!< Modbus Input register. */
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MB_PARAM_COIL, /*!< Modbus Coils. */
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MB_PARAM_DISCRETE, /*!< Modbus Discrete bits. */
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MB_PARAM_COUNT,
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MB_PARAM_UNKNOWN = 0xFF
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} mb_param_type_t;
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/*!
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* \brief Modbus serial transmission modes (RTU/ASCII).
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*/
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typedef enum {
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MB_MODE_RTU, /*!< RTU transmission mode. */
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MB_MODE_ASCII, /*!< ASCII transmission mode. */
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2020-07-21 12:34:04 -04:00
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MB_MODE_TCP, /*!< TCP communication mode. */
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MB_MODE_UDP /*!< UDP communication mode. */
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} mb_mode_type_t;
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/*!
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* \brief Modbus TCP type of address.
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*/
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typedef enum {
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MB_IPV4 = 0, /*!< TCP IPV4 addressing */
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MB_IPV6 = 1 /*!< TCP IPV6 addressing */
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} mb_tcp_addr_type_t;
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2018-10-19 09:51:27 -04:00
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/**
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* @brief Device communication structure to setup Modbus controller
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*/
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typedef union {
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// Serial communication structure
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struct {
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mb_mode_type_t mode; /*!< Modbus communication mode */
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uint8_t slave_addr; /*!< Modbus slave address field (dummy for master) */
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uart_port_t port; /*!< Modbus communication port (UART) number */
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uint32_t baudrate; /*!< Modbus baudrate */
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uart_parity_t parity; /*!< Modbus UART parity settings */
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2020-01-28 17:31:14 -05:00
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uint16_t dummy_port; /*!< Dummy field, unused */
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2018-10-19 09:51:27 -04:00
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};
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2020-07-21 12:34:04 -04:00
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// TCP/UDP communication structure
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2018-10-19 09:51:27 -04:00
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struct {
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2020-07-21 12:34:04 -04:00
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mb_mode_type_t ip_mode; /*!< Modbus communication mode */
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uint16_t ip_port; /*!< Modbus port */
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mb_tcp_addr_type_t ip_addr_type; /*!< Modbus address type */
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void* ip_addr; /*!< Modbus address table for connection */
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void* ip_netif_ptr; /*!< Modbus network interface */
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2018-10-19 09:51:27 -04:00
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};
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} mb_communication_info_t;
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/**
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* common interface method types
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*/
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2020-07-21 12:34:04 -04:00
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typedef esp_err_t (*iface_init)(void**); /*!< Interface method init */
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typedef esp_err_t (*iface_destroy)(void); /*!< Interface method destroy */
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typedef esp_err_t (*iface_setup)(void*); /*!< Interface method setup */
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typedef esp_err_t (*iface_start)(void); /*!< Interface method start */
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2018-10-19 09:51:27 -04:00
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2020-04-17 05:56:50 -04:00
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#ifdef __cplusplus
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}
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#endif
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2018-10-19 09:51:27 -04:00
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#endif // _MB_IFACE_COMMON_H
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