uint32_trx_done:1;/*The raw interrupt status bit for the i2s_rx_done_int interrupt*/
uint32_ttx_done:1;/*The raw interrupt status bit for the i2s_tx_done_int interrupt*/
uint32_trx_hung:1;/*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_ttx_hung:1;/*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_treserved4:28;/*Reserve*/
};
uint32_tval;
}int_raw;
union{
struct{
uint32_trx_done:1;/*The masked interrupt status bit for the i2s_rx_done_int interrupt*/
uint32_ttx_done:1;/*The masked interrupt status bit for the i2s_tx_done_int interrupt*/
uint32_trx_hung:1;/*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_ttx_hung:1;/*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_treserved4:28;/*Reserve*/
};
uint32_tval;
}int_st;
union{
struct{
uint32_trx_done:1;/*The interrupt enable bit for the i2s_rx_done_int interrupt*/
uint32_ttx_done:1;/*The interrupt enable bit for the i2s_tx_done_int interrupt*/
uint32_trx_hung:1;/*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_ttx_hung:1;/*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_treserved4:28;/*Reserve*/
};
uint32_tval;
}int_ena;
union{
struct{
uint32_trx_done:1;/*Set this bit to clear the i2s_rx_done_int interrupt*/
uint32_ttx_done:1;/*Set this bit to clear the i2s_tx_done_int interrupt*/
uint32_trx_hung:1;/*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_ttx_hung:1;/*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_treserved4:28;/*Reserve*/
};
uint32_tval;
}int_clr;
uint32_treserved_1c;
union{
struct{
uint32_trx_reset:1;/*Set this bit to reset receiver*/
uint32_trx_fifo_reset:1;/*Set this bit to reset Rx AFIFO*/
uint32_trx_start:1;/*Set this bit to start receiving data*/
uint32_trx_slave_mod:1;/*Set this bit to enable slave receiver mode*/
uint32_treserved4:1;/*Reserved*/
uint32_trx_mono:1;/*Set this bit to enable receiver in mono mode*/
uint32_treserved6:1;
uint32_trx_big_endian:1;/*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_trx_update:1;/*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_trx_mono_fst_vld:1;/*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
uint32_trx_pcm_bypass:1;/*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_trx_stop_mode:2;/*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
uint32_trx_left_align:1;/*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
uint32_trx_24_fill_en:1;/*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
uint32_trx_ws_idle_pol:1;/*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/
uint32_trx_bit_order:1;/*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/
uint32_ttx_reset:1;/*Set this bit to reset transmitter*/
uint32_ttx_fifo_reset:1;/*Set this bit to reset Tx AFIFO*/
uint32_ttx_start:1;/*Set this bit to start transmitting data*/
uint32_ttx_slave_mod:1;/*Set this bit to enable slave transmitter mode*/
uint32_treserved4:1;/*Reserved*/
uint32_ttx_mono:1;/*Set this bit to enable transmitter in mono mode*/
uint32_ttx_chan_equal:1;/*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
uint32_ttx_big_endian:1;/*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_ttx_update:1;/*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_ttx_mono_fst_vld:1;/*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
uint32_ttx_pcm_bypass:1;/*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_ttx_stop_en:1;/*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_treserved14:1;
uint32_ttx_left_align:1;/*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
uint32_ttx_24_fill_en:1;/*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
uint32_ttx_ws_idle_pol:1;/*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/
uint32_ttx_bit_order:1;/*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/
uint32_tmclk_sel:1;/*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
uint32_treserved30:2;/*Reserved*/
};
uint32_tval;
}rx_clkm_conf;
union{
struct{
uint32_ttx_clkm_div_num:8;/*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
uint32_ttx_iir_hp_mult12_5:3;/*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
uint32_ttx_iir_hp_mult12_0:3;/*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
uint32_treserved26:6;/*Reserved*/
};
uint32_tval;
}tx_pcm2pdm_conf1;
uint32_treserved_48;
uint32_treserved_4c;
union{
struct{
uint32_trx_tdm_pdm_chan0_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan1_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan2_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan3_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan4_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan5_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan6_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_pdm_chan7_en:1;/*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan8_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan9_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan10_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan11_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan12_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan13_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan14_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_chan15_en:1;/*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_trx_tdm_tot_chan_num:4;/*The total channel number of I2S TX TDM mode.*/
uint32_treserved20:12;/*Reserved*/
};
uint32_tval;
}rx_tdm_ctrl;
union{
struct{
uint32_ttx_tdm_chan0_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan1_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan2_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan3_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan4_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan5_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan6_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan7_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan8_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan9_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan10_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan11_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan12_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan13_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan14_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_chan15_en:1;/*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_ttx_tdm_tot_chan_num:4;/*The total channel number minus 1 of I2S TX TDM mode.*/
uint32_ttx_tdm_skip_msk_en:1;/*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
uint32_treserved21:11;/*Reserved*/
};
uint32_tval;
}tx_tdm_ctrl;
union{
struct{
uint32_trx_sd_in_dm:2;/*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved2:14;/* Reserved*/
uint32_trx_ws_out_dm:2;/*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved18:2;
uint32_trx_bck_out_dm:2;/*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved22:2;
uint32_trx_ws_in_dm:2;/*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved26:2;
uint32_trx_bck_in_dm:2;/*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved30:2;
};
uint32_tval;
}rx_timing;
union{
struct{
uint32_ttx_sd_out_dm:2;/*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved2:2;/* Reserved*/
uint32_ttx_sd1_out_dm:2;/*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved6:10;/* Reserved*/
uint32_ttx_ws_out_dm:2;/*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved18:2;/* Reserved*/
uint32_ttx_bck_out_dm:2;/*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved22:2;/* Reserved*/
uint32_ttx_ws_in_dm:2;/*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved26:2;/* Reserved*/
uint32_ttx_bck_in_dm:2;/*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_treserved30:2;/* Reserved*/
};
uint32_tval;
}tx_timing;
union{
struct{
uint32_tfifo_timeout:8;/*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_tfifo_timeout_shift:3;/*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_tfifo_timeout_ena:1;/*The enable bit for FIFO timeout*/
uint32_treserved12:20;/*Reserved*/
};
uint32_tval;
}lc_hung_conf;
union{
struct{
uint32_trx_eof_num:12;/*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_treserved12:20;/*Reserved*/
};
uint32_tval;
}rx_eof_num;
uint32_tconf_single_data;/*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
union{
struct{
uint32_ttx_idle:1;/*1: i2s_tx is idle state. 0: i2s_tx is working.*/
