2022-04-06 23:59:46 -04:00
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/*
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2023-02-08 04:02:21 -05:00
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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2022-04-06 23:59:46 -04:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/lock.h>
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#include "sdkconfig.h"
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#if CONFIG_RMT_ENABLE_DEBUG_LOG
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// The local log level must be defined before including esp_log.h
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// Set the maximum log level for this source file
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#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
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#endif
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#include "esp_log.h"
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#include "esp_check.h"
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#include "rmt_private.h"
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#include "clk_ctrl_os.h"
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#include "soc/rtc.h"
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#include "soc/rmt_periph.h"
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#include "hal/rmt_ll.h"
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#include "driver/gpio.h"
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2023-04-23 03:49:59 -04:00
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#include "esp_clk_tree.h"
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2022-04-06 23:59:46 -04:00
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#include "esp_private/periph_ctrl.h"
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static const char *TAG = "rmt";
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typedef struct rmt_platform_t {
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_lock_t mutex; // platform level mutex lock
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rmt_group_t *groups[SOC_RMT_GROUPS]; // array of RMT group instances
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int group_ref_counts[SOC_RMT_GROUPS]; // reference count used to protect group install/uninstall
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} rmt_platform_t;
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static rmt_platform_t s_platform; // singleton platform
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rmt_group_t *rmt_acquire_group_handle(int group_id)
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{
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bool new_group = false;
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rmt_group_t *group = NULL;
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// prevent install rmt group concurrently
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_lock_acquire(&s_platform.mutex);
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if (!s_platform.groups[group_id]) {
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group = heap_caps_calloc(1, sizeof(rmt_group_t), RMT_MEM_ALLOC_CAPS);
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if (group) {
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new_group = true;
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s_platform.groups[group_id] = group;
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group->group_id = group_id;
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group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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// initial occupy_mask: 1111...100...0
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group->occupy_mask = UINT32_MAX & ~((1 << SOC_RMT_CHANNELS_PER_GROUP) - 1);
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// group clock won't be configured at this stage, it will be set when allocate the first channel
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2022-06-22 06:08:25 -04:00
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group->clk_src = 0;
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2022-04-06 23:59:46 -04:00
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// enable APB access RMT registers
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periph_module_enable(rmt_periph_signals.groups[group_id].module);
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2022-06-06 23:00:57 -04:00
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periph_module_reset(rmt_periph_signals.groups[group_id].module);
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2023-08-29 05:56:03 -04:00
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// "uninitialize" group intr_priority, read comments in `rmt_new_tx_channel()` for detail
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group->intr_priority = RMT_GROUP_INTR_PRIORITY_UNINITALIZED;
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2022-04-06 23:59:46 -04:00
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// hal layer initialize
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rmt_hal_init(&group->hal);
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}
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} else { // group already install
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group = s_platform.groups[group_id];
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}
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if (group) {
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// someone acquired the group handle means we have a new object that refer to this group
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s_platform.group_ref_counts[group_id]++;
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}
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_lock_release(&s_platform.mutex);
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if (new_group) {
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2022-08-04 01:08:48 -04:00
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ESP_LOGD(TAG, "new group(%d) at %p, occupy=%"PRIx32, group_id, group, group->occupy_mask);
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2022-04-06 23:59:46 -04:00
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}
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return group;
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}
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void rmt_release_group_handle(rmt_group_t *group)
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{
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int group_id = group->group_id;
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2022-09-13 03:54:05 -04:00
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rmt_clock_source_t clk_src = group->clk_src;
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2022-04-06 23:59:46 -04:00
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bool do_deinitialize = false;
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_lock_acquire(&s_platform.mutex);
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s_platform.group_ref_counts[group_id]--;
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if (s_platform.group_ref_counts[group_id] == 0) {
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do_deinitialize = true;
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s_platform.groups[group_id] = NULL;
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// hal layer deinitialize
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rmt_hal_deinit(&group->hal);
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periph_module_disable(rmt_periph_signals.groups[group_id].module);
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free(group);
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}
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_lock_release(&s_platform.mutex);
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2022-09-13 03:54:05 -04:00
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switch (clk_src) {
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#if SOC_RMT_SUPPORT_RC_FAST
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case RMT_CLK_SRC_RC_FAST:
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periph_rtc_dig_clk8m_disable();
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break;
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#endif // SOC_RMT_SUPPORT_RC_FAST
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default:
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break;
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}
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2022-04-06 23:59:46 -04:00
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if (do_deinitialize) {
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ESP_LOGD(TAG, "del group(%d)", group_id);
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}
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}
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esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t clk_src)
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{
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esp_err_t ret = ESP_OK;
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rmt_group_t *group = chan->group;
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int channel_id = chan->channel_id;
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uint32_t periph_src_clk_hz = 0;
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bool clock_selection_conflict = false;
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// check if we need to update the group clock source, group clock source is shared by all channels
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portENTER_CRITICAL(&group->spinlock);
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2022-06-22 06:08:25 -04:00
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if (group->clk_src == 0) {
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2022-04-06 23:59:46 -04:00
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group->clk_src = clk_src;
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} else {
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clock_selection_conflict = (group->clk_src != clk_src);
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}
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portEXIT_CRITICAL(&group->spinlock);
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ESP_RETURN_ON_FALSE(!clock_selection_conflict, ESP_ERR_INVALID_STATE, TAG,
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"group clock conflict, already is %d but attempt to %d", group->clk_src, clk_src);
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2023-02-08 04:02:21 -05:00
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// TODO: [clk_tree] to use a generic clock enable/disable or acquire/release function for all clock source
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2022-04-06 23:59:46 -04:00
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#if SOC_RMT_SUPPORT_RC_FAST
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2023-02-08 04:02:21 -05:00
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if (clk_src == RMT_CLK_SRC_RC_FAST) {
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// RC_FAST clock is not enabled automatically on start up, we enable it here manually.
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// Note there's a ref count in the enable/disable function, we must call them in pair in the driver.
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2022-04-06 23:59:46 -04:00
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periph_rtc_dig_clk8m_enable();
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2023-02-08 04:02:21 -05:00
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}
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2022-04-06 23:59:46 -04:00
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#endif // SOC_RMT_SUPPORT_RC_FAST
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2023-02-08 04:02:21 -05:00
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// get clock source frequency
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2023-04-23 03:49:59 -04:00
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ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz),
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2023-02-08 04:02:21 -05:00
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TAG, "get clock source frequency failed");
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#if CONFIG_PM_ENABLE
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2023-09-26 01:33:25 -04:00
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// if DMA is not used, we're using CPU to push the data to the RMT FIFO
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// if the CPU frequency goes down, the transfer+encoding scheme could be unstable because CPU can't fill the data in time
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// so, choose ESP_PM_CPU_FREQ_MAX lock for non-dma mode
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// otherwise, chose lock type based on the clock source
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esp_pm_lock_type_t pm_lock_type = chan->dma_chan ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_CPU_FREQ_MAX;
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2023-02-08 04:02:21 -05:00
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#if SOC_RMT_SUPPORT_APB
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if (clk_src == RMT_CLK_SRC_APB) {
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// APB clock frequency can be changed during DFS
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pm_lock_type = ESP_PM_APB_FREQ_MAX;
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2022-04-06 23:59:46 -04:00
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}
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2023-02-08 04:02:21 -05:00
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#endif // SOC_RMT_SUPPORT_APB
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2023-09-26 01:33:25 -04:00
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sprintf(chan->pm_lock_name, "rmt_%d_%d", group->group_id, channel_id); // e.g. rmt_0_0
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ret = esp_pm_lock_create(pm_lock_type, 0, chan->pm_lock_name, &chan->pm_lock);
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ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed");
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2023-02-08 04:02:21 -05:00
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#endif // CONFIG_PM_ENABLE
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2022-04-06 23:59:46 -04:00
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// no division for group clock source, to achieve highest resolution
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rmt_ll_set_group_clock_src(group->hal.regs, channel_id, clk_src, 1, 1, 0);
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group->resolution_hz = periph_src_clk_hz;
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2022-08-04 01:08:48 -04:00
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ESP_LOGD(TAG, "group clock resolution:%"PRIu32, group->resolution_hz);
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2022-04-06 23:59:46 -04:00
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return ret;
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}
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2023-02-15 01:44:58 -05:00
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esp_err_t rmt_get_channel_id(rmt_channel_handle_t channel, int *ret_id)
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{
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ESP_RETURN_ON_FALSE(channel && ret_id, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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*ret_id = channel->channel_id;
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return ESP_OK;
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}
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2022-04-06 23:59:46 -04:00
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esp_err_t rmt_apply_carrier(rmt_channel_handle_t channel, const rmt_carrier_config_t *config)
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{
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// specially, we allow config to be NULL, means to disable the carrier submodule
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ESP_RETURN_ON_FALSE(channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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return channel->set_carrier_action(channel, config);
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}
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esp_err_t rmt_del_channel(rmt_channel_handle_t channel)
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{
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ESP_RETURN_ON_FALSE(channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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ESP_RETURN_ON_FALSE(channel->fsm == RMT_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state");
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gpio_reset_pin(channel->gpio_num);
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return channel->del(channel);
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}
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esp_err_t rmt_enable(rmt_channel_handle_t channel)
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{
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ESP_RETURN_ON_FALSE(channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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ESP_RETURN_ON_FALSE(channel->fsm == RMT_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state");
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return channel->enable(channel);
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}
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esp_err_t rmt_disable(rmt_channel_handle_t channel)
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{
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ESP_RETURN_ON_FALSE(channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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ESP_RETURN_ON_FALSE(channel->fsm == RMT_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "channel not in enable state");
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return channel->disable(channel);
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}
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2023-08-29 05:56:03 -04:00
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bool rmt_set_intr_priority_to_group(rmt_group_t *group, int intr_priority)
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{
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bool priority_conflict = false;
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portENTER_CRITICAL(&group->spinlock);
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if (group->intr_priority == RMT_GROUP_INTR_PRIORITY_UNINITALIZED) {
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// intr_priority never allocated, accept user's value unconditionally
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// intr_priority could only be set once here
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group->intr_priority = intr_priority;
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} else {
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// group intr_priority already specified
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// If interrupt priority specified before, it CANNOT BE CHANGED until `rmt_release_group_handle()` called
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// So we have to check if the new priority specified conflicts with the old one
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if (intr_priority) {
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// User specified intr_priority, check if conflict or not
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// Even though the `group->intr_priority` is 0, an intr_priority must have been specified automatically too,
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// although we do not know it exactly now, so specifying the intr_priority again might also cause conflict.
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// So no matter if `group->intr_priority` is 0 or not, we have to check.
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// Value `0` of `group->intr_priority` means "unknown", NOT "unspecified"!
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if (intr_priority != (group->intr_priority)) {
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// intr_priority conflicts!
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priority_conflict = true;
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}
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}
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// else do nothing
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// user did not specify intr_priority, then keep the old priority
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// We'll use the `RMT_INTR_ALLOC_FLAG | RMT_ALLOW_INTR_PRIORITY_MASK`, which should always success
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}
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// The `group->intr_priority` will not change any longer, even though another task tries to modify it.
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// So we could exit critical here safely.
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portEXIT_CRITICAL(&group->spinlock);
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return priority_conflict;
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}
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int rmt_get_isr_flags(rmt_group_t *group) {
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int isr_flags = RMT_INTR_ALLOC_FLAG;
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if (group->intr_priority) {
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// Use user-specified priority bit
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isr_flags |= (1 << (group->intr_priority));
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} else {
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// Allow all LOWMED priority bits
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isr_flags |= RMT_ALLOW_INTR_PRIORITY_MASK;
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}
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return isr_flags;
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}
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