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/*
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* SPDX - FileCopyrightText : 2017 - 2024 Espressif Systems ( Shanghai ) CO LTD
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*
* SPDX - License - Identifier : Apache - 2.0
*/
# include "sdkconfig.h"
# include "esp_efuse.h"
# include <assert.h>
# include "esp_efuse_table.h"
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// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
// To show efuse_table run the command 'show_efuse_table'.
static const esp_efuse_desc_t WR_DIS [ ] = {
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{ EFUSE_BLK0 , 0 , 32 } , // [] Disable programming of individual eFuses,
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} ;
static const esp_efuse_desc_t WR_DIS_RD_DIS [ ] = {
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{ EFUSE_BLK0 , 0 , 1 } , // [] wr_dis of RD_DIS,
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} ;
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static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of KM_RND_SWITCH_CYCLE,
} ;
static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of KM_DEPLOY_ONLY_ONCE,
} ;
static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY,
} ;
static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY,
} ;
static const esp_efuse_desc_t WR_DIS_XTS_KEY_LENGTH_256 [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of XTS_KEY_LENGTH_256,
} ;
static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of LOCK_KM_KEY,
} ;
static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE [ ] = {
{ EFUSE_BLK0 , 1 , 1 } , // [] wr_dis of KM_DISABLE_DEPLOY_MODE,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_USB_JTAG,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_FORCE_DOWNLOAD,
} ;
static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_TWAI [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_TWAI,
} ;
static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of JTAG_SEL_ENABLE,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_PAD_JTAG,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
} ;
static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of WDT_DELAY_SEL,
} ;
static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of HYS_EN_PAD,
} ;
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_0 [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of PXA0_TIEH_SEL_0,
} ;
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_1 [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of PXA0_TIEH_SEL_1,
} ;
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_2 [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of PXA0_TIEH_SEL_2,
} ;
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_3 [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of PXA0_TIEH_SEL_3,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_WDT [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_WDT,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_SWD [ ] = {
{ EFUSE_BLK0 , 2 , 1 } , // [] wr_dis of DIS_SWD,
} ;
static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL [ ] = {
{ EFUSE_BLK0 , 3 , 1 } , // [] wr_dis of HP_PWR_SRC_SEL,
} ;
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static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT [ ] = {
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{ EFUSE_BLK0 , 4 , 1 } , // [] wr_dis of SPI_BOOT_CRYPT_CNT,
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} ;
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0 [ ] = {
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{ EFUSE_BLK0 , 5 , 1 } , // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
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} ;
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1 [ ] = {
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{ EFUSE_BLK0 , 6 , 1 } , // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
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} ;
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2 [ ] = {
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{ EFUSE_BLK0 , 7 , 1 } , // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
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} ;
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static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0 [ ] = {
{ EFUSE_BLK0 , 8 , 1 } , // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
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} ;
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static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1 [ ] = {
{ EFUSE_BLK0 , 9 , 1 } , // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
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} ;
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static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2 [ ] = {
{ EFUSE_BLK0 , 10 , 1 } , // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
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} ;
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static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3 [ ] = {
{ EFUSE_BLK0 , 11 , 1 } , // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
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} ;
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static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4 [ ] = {
{ EFUSE_BLK0 , 12 , 1 } , // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
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} ;
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static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5 [ ] = {
{ EFUSE_BLK0 , 13 , 1 } , // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
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} ;
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static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL [ ] = {
{ EFUSE_BLK0 , 14 , 1 } , // [] wr_dis of SEC_DPA_LEVEL,
} ;
static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE [ ] = {
{ EFUSE_BLK0 , 14 , 1 } , // [] wr_dis of CRYPT_DPA_ENABLE,
} ;
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static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN [ ] = {
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{ EFUSE_BLK0 , 15 , 1 } , // [] wr_dis of SECURE_BOOT_EN,
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} ;
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static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE [ ] = {
{ EFUSE_BLK0 , 16 , 1 } , // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
} ;
static const esp_efuse_desc_t WR_DIS_ECDSA_ENABLE_SOFT_K [ ] = {
{ EFUSE_BLK0 , 17 , 1 } , // [] wr_dis of ECDSA_ENABLE_SOFT_K,
} ;
static const esp_efuse_desc_t WR_DIS_FLASH_TYPE [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of FLASH_TYPE,
} ;
static const esp_efuse_desc_t WR_DIS_FLASH_PAGE_SIZE [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of FLASH_PAGE_SIZE,
} ;
static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of FLASH_ECC_EN,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE,
} ;
static const esp_efuse_desc_t WR_DIS_FLASH_TPUW [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of FLASH_TPUW,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of DIS_DOWNLOAD_MODE,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of DIS_DIRECT_BOOT,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
} ;
static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,
} ;
static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
} ;
static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of UART_PRINT_CONTROL,
} ;
static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of FORCE_SEND_RESUME,
} ;
static const esp_efuse_desc_t WR_DIS_SECURE_VERSION [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of SECURE_VERSION,
} ;
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE [ ] = {
{ EFUSE_BLK0 , 18 , 1 } , // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
} ;
static const esp_efuse_desc_t WR_DIS_KM_HUK_GEN_STATE [ ] = {
{ EFUSE_BLK0 , 19 , 1 } , // [] wr_dis of KM_HUK_GEN_STATE,
} ;
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static const esp_efuse_desc_t WR_DIS_BLK1 [ ] = {
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{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of BLOCK1,
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} ;
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static const esp_efuse_desc_t WR_DIS_MAC [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
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} ;
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static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of WAFER_VERSION_MINOR,
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} ;
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static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of WAFER_VERSION_MAJOR,
} ;
static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
} ;
static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
} ;
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of BLK_VERSION_MINOR,
} ;
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of BLK_VERSION_MAJOR,
} ;
static const esp_efuse_desc_t WR_DIS_PSRAM_CAP [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of PSRAM_CAP,
} ;
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static const esp_efuse_desc_t WR_DIS_TEMP [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of TEMP,
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} ;
static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of PSRAM_VENDOR,
} ;
static const esp_efuse_desc_t WR_DIS_PKG_VERSION [ ] = {
{ EFUSE_BLK0 , 20 , 1 } , // [] wr_dis of PKG_VERSION,
} ;
static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1 [ ] = {
{ EFUSE_BLK0 , 21 , 1 } , // [] wr_dis of BLOCK2,
} ;
static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID [ ] = {
{ EFUSE_BLK0 , 21 , 1 } , // [] wr_dis of OPTIONAL_UNIQUE_ID,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA [ ] = {
{ EFUSE_BLK0 , 22 , 1 } , // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
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} ;
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static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC [ ] = {
{ EFUSE_BLK0 , 22 , 1 } , // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0 [ ] = {
{ EFUSE_BLK0 , 23 , 1 } , // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1 [ ] = {
{ EFUSE_BLK0 , 24 , 1 } , // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2 [ ] = {
{ EFUSE_BLK0 , 25 , 1 } , // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3 [ ] = {
{ EFUSE_BLK0 , 26 , 1 } , // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4 [ ] = {
{ EFUSE_BLK0 , 27 , 1 } , // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5 [ ] = {
{ EFUSE_BLK0 , 28 , 1 } , // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
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} ;
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static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2 [ ] = {
{ EFUSE_BLK0 , 29 , 1 } , // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
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} ;
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static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS [ ] = {
{ EFUSE_BLK0 , 30 , 1 } , // [] wr_dis of USB_DEVICE_EXCHG_PINS,
} ;
static const esp_efuse_desc_t WR_DIS_USB_OTG11_EXCHG_PINS [ ] = {
{ EFUSE_BLK0 , 30 , 1 } , // [] wr_dis of USB_OTG11_EXCHG_PINS,
} ;
static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL [ ] = {
{ EFUSE_BLK0 , 30 , 1 } , // [] wr_dis of USB_PHY_SEL,
} ;
static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG [ ] = {
{ EFUSE_BLK0 , 31 , 1 } , // [] wr_dis of SOFT_DIS_JTAG,
} ;
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static const esp_efuse_desc_t RD_DIS [ ] = {
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{ EFUSE_BLK0 , 32 , 7 } , // [] Disable reading from BlOCK4-10,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0 [ ] = {
{ EFUSE_BLK0 , 32 , 1 } , // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1 [ ] = {
{ EFUSE_BLK0 , 33 , 1 } , // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2 [ ] = {
{ EFUSE_BLK0 , 34 , 1 } , // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3 [ ] = {
{ EFUSE_BLK0 , 35 , 1 } , // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4 [ ] = {
{ EFUSE_BLK0 , 36 , 1 } , // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5 [ ] = {
{ EFUSE_BLK0 , 37 , 1 } , // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
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} ;
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static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2 [ ] = {
{ EFUSE_BLK0 , 38 , 1 } , // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
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} ;
static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS [ ] = {
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{ EFUSE_BLK0 , 39 , 1 } , // [] Enable usb device exchange pins of D+ and D-,
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} ;
static const esp_efuse_desc_t USB_OTG11_EXCHG_PINS [ ] = {
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{ EFUSE_BLK0 , 40 , 1 } , // [] Enable usb otg11 exchange pins of D+ and D-,
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} ;
static const esp_efuse_desc_t DIS_USB_JTAG [ ] = {
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{ EFUSE_BLK0 , 41 , 1 } , // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t POWERGLITCH_EN [ ] = {
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{ EFUSE_BLK0 , 42 , 1 } , // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled,
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} ;
static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD [ ] = {
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{ EFUSE_BLK0 , 44 , 1 } , // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled,
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} ;
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static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS [ ] = {
{ EFUSE_BLK0 , 45 , 1 } , // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download,
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} ;
static const esp_efuse_desc_t DIS_TWAI [ ] = {
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{ EFUSE_BLK0 , 46 , 1 } , // [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t JTAG_SEL_ENABLE [ ] = {
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{ EFUSE_BLK0 , 47 , 1 } , // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled,
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} ;
static const esp_efuse_desc_t SOFT_DIS_JTAG [ ] = {
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{ EFUSE_BLK0 , 48 , 3 } , // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled,
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} ;
static const esp_efuse_desc_t DIS_PAD_JTAG [ ] = {
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{ EFUSE_BLK0 , 51 , 1 } , // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT [ ] = {
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{ EFUSE_BLK0 , 52 , 1 } , // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled,
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} ;
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static const esp_efuse_desc_t USB_PHY_SEL [ ] = {
{ EFUSE_BLK0 , 57 , 1 } , // [] TBD,
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} ;
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static const esp_efuse_desc_t KM_HUK_GEN_STATE [ ] = {
{ EFUSE_BLK0 , 58 , 9 } , // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid,
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} ;
static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE [ ] = {
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{ EFUSE_BLK0 , 67 , 2 } , // [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles,
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} ;
static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE [ ] = {
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{ EFUSE_BLK0 , 69 , 4 } , // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds,
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} ;
static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY [ ] = {
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{ EFUSE_BLK0 , 73 , 4 } , // [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds,
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} ;
static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY [ ] = {
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{ EFUSE_BLK0 , 77 , 1 } , // [] Set this bit to disable software written init key; and force use efuse_init_key,
} ;
static const esp_efuse_desc_t XTS_KEY_LENGTH_256 [ ] = {
{ EFUSE_BLK0 , 78 , 1 } , // [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key,
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} ;
static const esp_efuse_desc_t WDT_DELAY_SEL [ ] = {
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{ EFUSE_BLK0 , 80 , 2 } , // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected,
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} ;
static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT [ ] = {
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{ EFUSE_BLK0 , 82 , 3 } , // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
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} ;
static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0 [ ] = {
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{ EFUSE_BLK0 , 85 , 1 } , // [] Revoke 1st secure boot key,
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} ;
static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1 [ ] = {
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{ EFUSE_BLK0 , 86 , 1 } , // [] Revoke 2nd secure boot key,
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} ;
static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2 [ ] = {
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{ EFUSE_BLK0 , 87 , 1 } , // [] Revoke 3rd secure boot key,
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} ;
static const esp_efuse_desc_t KEY_PURPOSE_0 [ ] = {
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{ EFUSE_BLK0 , 88 , 4 } , // [KEY0_PURPOSE] Represents the purpose of Key0,
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} ;
static const esp_efuse_desc_t KEY_PURPOSE_1 [ ] = {
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{ EFUSE_BLK0 , 92 , 4 } , // [KEY1_PURPOSE] Represents the purpose of Key1,
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} ;
static const esp_efuse_desc_t KEY_PURPOSE_2 [ ] = {
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{ EFUSE_BLK0 , 96 , 4 } , // [KEY2_PURPOSE] Represents the purpose of Key2,
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} ;
static const esp_efuse_desc_t KEY_PURPOSE_3 [ ] = {
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{ EFUSE_BLK0 , 100 , 4 } , // [KEY3_PURPOSE] Represents the purpose of Key3,
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} ;
static const esp_efuse_desc_t KEY_PURPOSE_4 [ ] = {
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{ EFUSE_BLK0 , 104 , 4 } , // [KEY4_PURPOSE] Represents the purpose of Key4,
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} ;
static const esp_efuse_desc_t KEY_PURPOSE_5 [ ] = {
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{ EFUSE_BLK0 , 108 , 4 } , // [KEY5_PURPOSE] Represents the purpose of Key5,
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} ;
static const esp_efuse_desc_t SEC_DPA_LEVEL [ ] = {
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{ EFUSE_BLK0 , 112 , 2 } , // [] Represents the spa secure level by configuring the clock random divide mode,
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} ;
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static const esp_efuse_desc_t ECDSA_ENABLE_SOFT_K [ ] = {
{ EFUSE_BLK0 , 114 , 1 } , // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used,
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} ;
static const esp_efuse_desc_t CRYPT_DPA_ENABLE [ ] = {
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{ EFUSE_BLK0 , 115 , 1 } , // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled,
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} ;
static const esp_efuse_desc_t SECURE_BOOT_EN [ ] = {
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{ EFUSE_BLK0 , 116 , 1 } , // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled,
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} ;
static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE [ ] = {
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{ EFUSE_BLK0 , 117 , 1 } , // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled,
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} ;
static const esp_efuse_desc_t FLASH_TYPE [ ] = {
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{ EFUSE_BLK0 , 119 , 1 } , // [] The type of interfaced flash. 0: four data lines; 1: eight data lines,
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} ;
static const esp_efuse_desc_t FLASH_PAGE_SIZE [ ] = {
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{ EFUSE_BLK0 , 120 , 2 } , // [] Set flash page size,
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} ;
static const esp_efuse_desc_t FLASH_ECC_EN [ ] = {
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{ EFUSE_BLK0 , 122 , 1 } , // [] Set this bit to enable ecc for flash boot,
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} ;
static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE [ ] = {
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{ EFUSE_BLK0 , 123 , 1 } , // [] Set this bit to disable download via USB-OTG,
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} ;
static const esp_efuse_desc_t FLASH_TPUW [ ] = {
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{ EFUSE_BLK0 , 124 , 4 } , // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
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} ;
static const esp_efuse_desc_t DIS_DOWNLOAD_MODE [ ] = {
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{ EFUSE_BLK0 , 128 , 1 } , // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t DIS_DIRECT_BOOT [ ] = {
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{ EFUSE_BLK0 , 129 , 1 } , // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT [ ] = {
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{ EFUSE_BLK0 , 130 , 1 } , // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled,
} ;
static const esp_efuse_desc_t LOCK_KM_KEY [ ] = {
{ EFUSE_BLK0 , 131 , 1 } , // [] TBD,
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} ;
static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE [ ] = {
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{ EFUSE_BLK0 , 132 , 1 } , // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD [ ] = {
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{ EFUSE_BLK0 , 133 , 1 } , // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled,
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} ;
static const esp_efuse_desc_t UART_PRINT_CONTROL [ ] = {
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{ EFUSE_BLK0 , 134 , 2 } , // [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing,
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} ;
static const esp_efuse_desc_t FORCE_SEND_RESUME [ ] = {
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{ EFUSE_BLK0 , 136 , 1 } , // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced,
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} ;
static const esp_efuse_desc_t SECURE_VERSION [ ] = {
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{ EFUSE_BLK0 , 137 , 16 } , // [] Represents the version used by ESP-IDF anti-rollback feature,
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} ;
static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE [ ] = {
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{ EFUSE_BLK0 , 153 , 1 } , // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled,
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} ;
static const esp_efuse_desc_t HYS_EN_PAD [ ] = {
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{ EFUSE_BLK0 , 154 , 1 } , // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled,
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} ;
static const esp_efuse_desc_t DCDC_VSET [ ] = {
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{ EFUSE_BLK0 , 155 , 5 } , // [] Set the dcdc voltage default,
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} ;
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static const esp_efuse_desc_t PXA0_TIEH_SEL_0 [ ] = {
{ EFUSE_BLK0 , 160 , 2 } , // [] TBD,
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} ;
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static const esp_efuse_desc_t PXA0_TIEH_SEL_1 [ ] = {
{ EFUSE_BLK0 , 162 , 2 } , // [] TBD,
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} ;
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static const esp_efuse_desc_t PXA0_TIEH_SEL_2 [ ] = {
{ EFUSE_BLK0 , 164 , 2 } , // [] TBD,
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} ;
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static const esp_efuse_desc_t PXA0_TIEH_SEL_3 [ ] = {
{ EFUSE_BLK0 , 166 , 2 } , // [] TBD,
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} ;
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static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE [ ] = {
{ EFUSE_BLK0 , 168 , 4 } , // [] TBD,
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} ;
static const esp_efuse_desc_t HP_PWR_SRC_SEL [ ] = {
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{ EFUSE_BLK0 , 178 , 1 } , // [] HP system power source select. 0:LDO. 1: DCDC,
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} ;
static const esp_efuse_desc_t DCDC_VSET_EN [ ] = {
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{ EFUSE_BLK0 , 179 , 1 } , // [] Select dcdc vset use efuse_dcdc_vset,
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} ;
static const esp_efuse_desc_t DIS_WDT [ ] = {
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{ EFUSE_BLK0 , 180 , 1 } , // [] Set this bit to disable watch dog,
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} ;
static const esp_efuse_desc_t DIS_SWD [ ] = {
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{ EFUSE_BLK0 , 181 , 1 } , // [] Set this bit to disable super-watchdog,
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} ;
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static const esp_efuse_desc_t MAC [ ] = {
{ EFUSE_BLK1 , 40 , 8 } , // [MAC_FACTORY] MAC address,
{ EFUSE_BLK1 , 32 , 8 } , // [MAC_FACTORY] MAC address,
{ EFUSE_BLK1 , 24 , 8 } , // [MAC_FACTORY] MAC address,
{ EFUSE_BLK1 , 16 , 8 } , // [MAC_FACTORY] MAC address,
{ EFUSE_BLK1 , 8 , 8 } , // [MAC_FACTORY] MAC address,
{ EFUSE_BLK1 , 0 , 8 } , // [MAC_FACTORY] MAC address,
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} ;
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static const esp_efuse_desc_t WAFER_VERSION_MINOR [ ] = {
{ EFUSE_BLK1 , 64 , 4 } , // [] Minor chip version,
} ;
static const esp_efuse_desc_t WAFER_VERSION_MAJOR [ ] = {
{ EFUSE_BLK1 , 68 , 2 } , // [] Major chip version,
} ;
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR [ ] = {
{ EFUSE_BLK1 , 70 , 1 } , // [] Disables check of wafer version major,
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} ;
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static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR [ ] = {
{ EFUSE_BLK1 , 71 , 1 } , // [] Disables check of blk version major,
} ;
static const esp_efuse_desc_t BLK_VERSION_MINOR [ ] = {
{ EFUSE_BLK1 , 72 , 3 } , // [] BLK_VERSION_MINOR of BLOCK2,
} ;
static const esp_efuse_desc_t BLK_VERSION_MAJOR [ ] = {
{ EFUSE_BLK1 , 75 , 2 } , // [] BLK_VERSION_MAJOR of BLOCK2,
} ;
static const esp_efuse_desc_t PSRAM_CAP [ ] = {
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{ EFUSE_BLK1 , 77 , 3 } , // [] PSRAM capacity,
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} ;
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static const esp_efuse_desc_t TEMP [ ] = {
{ EFUSE_BLK1 , 80 , 2 } , // [] Operating temperature of the ESP chip,
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} ;
static const esp_efuse_desc_t PSRAM_VENDOR [ ] = {
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{ EFUSE_BLK1 , 82 , 2 } , // [] PSRAM vendor,
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} ;
static const esp_efuse_desc_t PKG_VERSION [ ] = {
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{ EFUSE_BLK1 , 84 , 3 } , // [] Package version,
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} ;
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID [ ] = {
{ EFUSE_BLK2 , 0 , 128 } , // [] Optional unique 128-bit ID,
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} ;
static const esp_efuse_desc_t USER_DATA [ ] = {
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{ EFUSE_BLK3 , 0 , 256 } , // [BLOCK_USR_DATA] User data,
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} ;
static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM [ ] = {
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{ EFUSE_BLK3 , 200 , 48 } , // [MAC_CUSTOM CUSTOM_MAC] Custom MAC,
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} ;
static const esp_efuse_desc_t KEY0 [ ] = {
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{ EFUSE_BLK4 , 0 , 256 } , // [BLOCK_KEY0] Key0 or user data,
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} ;
static const esp_efuse_desc_t KEY1 [ ] = {
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{ EFUSE_BLK5 , 0 , 256 } , // [BLOCK_KEY1] Key1 or user data,
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} ;
static const esp_efuse_desc_t KEY2 [ ] = {
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{ EFUSE_BLK6 , 0 , 256 } , // [BLOCK_KEY2] Key2 or user data,
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} ;
static const esp_efuse_desc_t KEY3 [ ] = {
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{ EFUSE_BLK7 , 0 , 256 } , // [BLOCK_KEY3] Key3 or user data,
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} ;
static const esp_efuse_desc_t KEY4 [ ] = {
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{ EFUSE_BLK8 , 0 , 256 } , // [BLOCK_KEY4] Key4 or user data,
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} ;
static const esp_efuse_desc_t KEY5 [ ] = {
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{ EFUSE_BLK9 , 0 , 256 } , // [BLOCK_KEY5] Key5 or user data,
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} ;
static const esp_efuse_desc_t SYS_DATA_PART2 [ ] = {
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{ EFUSE_BLK10 , 0 , 256 } , // [BLOCK_SYS_DATA2] System data part 2 (reserved),
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} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS [ ] = {
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& WR_DIS [ 0 ] , // [] Disable programming of individual eFuses
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_RD_DIS [ ] = {
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& WR_DIS_RD_DIS [ 0 ] , // [] wr_dis of RD_DIS
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE [ ] = {
& WR_DIS_KM_RND_SWITCH_CYCLE [ 0 ] , // [] wr_dis of KM_RND_SWITCH_CYCLE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE [ ] = {
& WR_DIS_KM_DEPLOY_ONLY_ONCE [ 0 ] , // [] wr_dis of KM_DEPLOY_ONLY_ONCE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY [ ] = {
& WR_DIS_FORCE_USE_KEY_MANAGER_KEY [ 0 ] , // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY [ ] = {
& WR_DIS_FORCE_DISABLE_SW_INIT_KEY [ 0 ] , // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256 [ ] = {
& WR_DIS_XTS_KEY_LENGTH_256 [ 0 ] , // [] wr_dis of XTS_KEY_LENGTH_256
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_LOCK_KM_KEY [ ] = {
& WR_DIS_LOCK_KM_KEY [ 0 ] , // [] wr_dis of LOCK_KM_KEY
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE [ ] = {
& WR_DIS_KM_DISABLE_DEPLOY_MODE [ 0 ] , // [] wr_dis of KM_DISABLE_DEPLOY_MODE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_USB_JTAG [ ] = {
& WR_DIS_DIS_USB_JTAG [ 0 ] , // [] wr_dis of DIS_USB_JTAG
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD [ ] = {
& WR_DIS_DIS_FORCE_DOWNLOAD [ 0 ] , // [] wr_dis of DIS_FORCE_DOWNLOAD
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS [ ] = {
& WR_DIS_SPI_DOWNLOAD_MSPI_DIS [ 0 ] , // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_TWAI [ ] = {
& WR_DIS_DIS_TWAI [ 0 ] , // [] wr_dis of DIS_TWAI
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE [ ] = {
& WR_DIS_JTAG_SEL_ENABLE [ 0 ] , // [] wr_dis of JTAG_SEL_ENABLE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_PAD_JTAG [ ] = {
& WR_DIS_DIS_PAD_JTAG [ 0 ] , // [] wr_dis of DIS_PAD_JTAG
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT [ ] = {
& WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT [ 0 ] , // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_WDT_DELAY_SEL [ ] = {
& WR_DIS_WDT_DELAY_SEL [ 0 ] , // [] wr_dis of WDT_DELAY_SEL
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_HYS_EN_PAD [ ] = {
& WR_DIS_HYS_EN_PAD [ 0 ] , // [] wr_dis of HYS_EN_PAD
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0 [ ] = {
& WR_DIS_PXA0_TIEH_SEL_0 [ 0 ] , // [] wr_dis of PXA0_TIEH_SEL_0
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1 [ ] = {
& WR_DIS_PXA0_TIEH_SEL_1 [ 0 ] , // [] wr_dis of PXA0_TIEH_SEL_1
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2 [ ] = {
& WR_DIS_PXA0_TIEH_SEL_2 [ 0 ] , // [] wr_dis of PXA0_TIEH_SEL_2
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3 [ ] = {
& WR_DIS_PXA0_TIEH_SEL_3 [ 0 ] , // [] wr_dis of PXA0_TIEH_SEL_3
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_WDT [ ] = {
& WR_DIS_DIS_WDT [ 0 ] , // [] wr_dis of DIS_WDT
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_SWD [ ] = {
& WR_DIS_DIS_SWD [ 0 ] , // [] wr_dis of DIS_SWD
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL [ ] = {
& WR_DIS_HP_PWR_SRC_SEL [ 0 ] , // [] wr_dis of HP_PWR_SRC_SEL
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT [ ] = {
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& WR_DIS_SPI_BOOT_CRYPT_CNT [ 0 ] , // [] wr_dis of SPI_BOOT_CRYPT_CNT
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0 [ ] = {
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& WR_DIS_SECURE_BOOT_KEY_REVOKE0 [ 0 ] , // [] wr_dis of SECURE_BOOT_KEY_REVOKE0
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1 [ ] = {
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& WR_DIS_SECURE_BOOT_KEY_REVOKE1 [ 0 ] , // [] wr_dis of SECURE_BOOT_KEY_REVOKE1
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2 [ ] = {
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& WR_DIS_SECURE_BOOT_KEY_REVOKE2 [ 0 ] , // [] wr_dis of SECURE_BOOT_KEY_REVOKE2
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 [ ] = {
& WR_DIS_KEY_PURPOSE_0 [ 0 ] , // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 [ ] = {
& WR_DIS_KEY_PURPOSE_1 [ 0 ] , // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 [ ] = {
& WR_DIS_KEY_PURPOSE_2 [ 0 ] , // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 [ ] = {
& WR_DIS_KEY_PURPOSE_3 [ 0 ] , // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 [ ] = {
& WR_DIS_KEY_PURPOSE_4 [ 0 ] , // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 [ ] = {
& WR_DIS_KEY_PURPOSE_5 [ 0 ] , // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL [ ] = {
& WR_DIS_SEC_DPA_LEVEL [ 0 ] , // [] wr_dis of SEC_DPA_LEVEL
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE [ ] = {
& WR_DIS_CRYPT_DPA_ENABLE [ 0 ] , // [] wr_dis of CRYPT_DPA_ENABLE
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_BOOT_EN [ ] = {
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& WR_DIS_SECURE_BOOT_EN [ 0 ] , // [] wr_dis of SECURE_BOOT_EN
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE [ ] = {
& WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE [ 0 ] , // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K [ ] = {
& WR_DIS_ECDSA_ENABLE_SOFT_K [ 0 ] , // [] wr_dis of ECDSA_ENABLE_SOFT_K
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FLASH_TYPE [ ] = {
& WR_DIS_FLASH_TYPE [ 0 ] , // [] wr_dis of FLASH_TYPE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE [ ] = {
& WR_DIS_FLASH_PAGE_SIZE [ 0 ] , // [] wr_dis of FLASH_PAGE_SIZE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FLASH_ECC_EN [ ] = {
& WR_DIS_FLASH_ECC_EN [ 0 ] , // [] wr_dis of FLASH_ECC_EN
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE [ ] = {
& WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE [ 0 ] , // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FLASH_TPUW [ ] = {
& WR_DIS_FLASH_TPUW [ 0 ] , // [] wr_dis of FLASH_TPUW
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE [ ] = {
& WR_DIS_DIS_DOWNLOAD_MODE [ 0 ] , // [] wr_dis of DIS_DOWNLOAD_MODE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT [ ] = {
& WR_DIS_DIS_DIRECT_BOOT [ 0 ] , // [] wr_dis of DIS_DIRECT_BOOT
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT [ ] = {
& WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT [ 0 ] , // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE [ ] = {
& WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE [ 0 ] , // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD [ ] = {
& WR_DIS_ENABLE_SECURITY_DOWNLOAD [ 0 ] , // [] wr_dis of ENABLE_SECURITY_DOWNLOAD
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL [ ] = {
& WR_DIS_UART_PRINT_CONTROL [ 0 ] , // [] wr_dis of UART_PRINT_CONTROL
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME [ ] = {
& WR_DIS_FORCE_SEND_RESUME [ 0 ] , // [] wr_dis of FORCE_SEND_RESUME
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_VERSION [ ] = {
& WR_DIS_SECURE_VERSION [ 0 ] , // [] wr_dis of SECURE_VERSION
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE [ ] = {
& WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE [ 0 ] , // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE [ ] = {
& WR_DIS_KM_HUK_GEN_STATE [ 0 ] , // [] wr_dis of KM_HUK_GEN_STATE
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLK1 [ ] = {
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& WR_DIS_BLK1 [ 0 ] , // [] wr_dis of BLOCK1
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_MAC [ ] = {
& WR_DIS_MAC [ 0 ] , // [WR_DIS.MAC_FACTORY] wr_dis of MAC
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR [ ] = {
& WR_DIS_WAFER_VERSION_MINOR [ 0 ] , // [] wr_dis of WAFER_VERSION_MINOR
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR [ ] = {
& WR_DIS_WAFER_VERSION_MAJOR [ 0 ] , // [] wr_dis of WAFER_VERSION_MAJOR
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR [ ] = {
& WR_DIS_DISABLE_WAFER_VERSION_MAJOR [ 0 ] , // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR [ ] = {
& WR_DIS_DISABLE_BLK_VERSION_MAJOR [ 0 ] , // [] wr_dis of DISABLE_BLK_VERSION_MAJOR
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR [ ] = {
& WR_DIS_BLK_VERSION_MINOR [ 0 ] , // [] wr_dis of BLK_VERSION_MINOR
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR [ ] = {
& WR_DIS_BLK_VERSION_MAJOR [ 0 ] , // [] wr_dis of BLK_VERSION_MAJOR
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PSRAM_CAP [ ] = {
& WR_DIS_PSRAM_CAP [ 0 ] , // [] wr_dis of PSRAM_CAP
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_TEMP [ ] = {
& WR_DIS_TEMP [ 0 ] , // [] wr_dis of TEMP
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PSRAM_VENDOR [ ] = {
& WR_DIS_PSRAM_VENDOR [ 0 ] , // [] wr_dis of PSRAM_VENDOR
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_PKG_VERSION [ ] = {
& WR_DIS_PKG_VERSION [ 0 ] , // [] wr_dis of PKG_VERSION
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SYS_DATA_PART1 [ ] = {
& WR_DIS_SYS_DATA_PART1 [ 0 ] , // [] wr_dis of BLOCK2
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID [ ] = {
& WR_DIS_OPTIONAL_UNIQUE_ID [ 0 ] , // [] wr_dis of OPTIONAL_UNIQUE_ID
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_USR_DATA [ ] = {
& WR_DIS_BLOCK_USR_DATA [ 0 ] , // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_CUSTOM_MAC [ ] = {
& WR_DIS_CUSTOM_MAC [ 0 ] , // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_KEY0 [ ] = {
& WR_DIS_BLOCK_KEY0 [ 0 ] , // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_KEY1 [ ] = {
& WR_DIS_BLOCK_KEY1 [ 0 ] , // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_KEY2 [ ] = {
& WR_DIS_BLOCK_KEY2 [ 0 ] , // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_KEY3 [ ] = {
& WR_DIS_BLOCK_KEY3 [ 0 ] , // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_KEY4 [ ] = {
& WR_DIS_BLOCK_KEY4 [ 0 ] , // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_KEY5 [ ] = {
& WR_DIS_BLOCK_KEY5 [ 0 ] , // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 [ ] = {
& WR_DIS_BLOCK_SYS_DATA2 [ 0 ] , // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS [ ] = {
& WR_DIS_USB_DEVICE_EXCHG_PINS [ 0 ] , // [] wr_dis of USB_DEVICE_EXCHG_PINS
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS [ ] = {
& WR_DIS_USB_OTG11_EXCHG_PINS [ 0 ] , // [] wr_dis of USB_OTG11_EXCHG_PINS
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_USB_PHY_SEL [ ] = {
& WR_DIS_USB_PHY_SEL [ 0 ] , // [] wr_dis of USB_PHY_SEL
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG [ ] = {
& WR_DIS_SOFT_DIS_JTAG [ 0 ] , // [] wr_dis of SOFT_DIS_JTAG
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS [ ] = {
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& RD_DIS [ 0 ] , // [] Disable reading from BlOCK4-10
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_KEY0 [ ] = {
& RD_DIS_BLOCK_KEY0 [ 0 ] , // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_KEY1 [ ] = {
& RD_DIS_BLOCK_KEY1 [ 0 ] , // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_KEY2 [ ] = {
& RD_DIS_BLOCK_KEY2 [ 0 ] , // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_KEY3 [ ] = {
& RD_DIS_BLOCK_KEY3 [ 0 ] , // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_KEY4 [ ] = {
& RD_DIS_BLOCK_KEY4 [ 0 ] , // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_KEY5 [ ] = {
& RD_DIS_BLOCK_KEY5 [ 0 ] , // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 [ ] = {
& RD_DIS_BLOCK_SYS_DATA2 [ 0 ] , // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_USB_DEVICE_EXCHG_PINS [ ] = {
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& USB_DEVICE_EXCHG_PINS [ 0 ] , // [] Enable usb device exchange pins of D+ and D-
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_USB_OTG11_EXCHG_PINS [ ] = {
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& USB_OTG11_EXCHG_PINS [ 0 ] , // [] Enable usb otg11 exchange pins of D+ and D-
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_USB_JTAG [ ] = {
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& DIS_USB_JTAG [ 0 ] , // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_POWERGLITCH_EN [ ] = {
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& POWERGLITCH_EN [ 0 ] , // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_FORCE_DOWNLOAD [ ] = {
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& DIS_FORCE_DOWNLOAD [ 0 ] , // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS [ ] = {
& SPI_DOWNLOAD_MSPI_DIS [ 0 ] , // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_TWAI [ ] = {
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& DIS_TWAI [ 0 ] , // [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_JTAG_SEL_ENABLE [ ] = {
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& JTAG_SEL_ENABLE [ 0 ] , // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SOFT_DIS_JTAG [ ] = {
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& SOFT_DIS_JTAG [ 0 ] , // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_PAD_JTAG [ ] = {
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& DIS_PAD_JTAG [ 0 ] , // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT [ ] = {
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& DIS_DOWNLOAD_MANUAL_ENCRYPT [ 0 ] , // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_USB_PHY_SEL [ ] = {
& USB_PHY_SEL [ 0 ] , // [] TBD
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_KM_HUK_GEN_STATE [ ] = {
& KM_HUK_GEN_STATE [ 0 ] , // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KM_RND_SWITCH_CYCLE [ ] = {
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& KM_RND_SWITCH_CYCLE [ 0 ] , // [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KM_DEPLOY_ONLY_ONCE [ ] = {
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& KM_DEPLOY_ONLY_ONCE [ 0 ] , // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY [ ] = {
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& FORCE_USE_KEY_MANAGER_KEY [ 0 ] , // [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY [ ] = {
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& FORCE_DISABLE_SW_INIT_KEY [ 0 ] , // [] Set this bit to disable software written init key; and force use efuse_init_key
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_XTS_KEY_LENGTH_256 [ ] = {
& XTS_KEY_LENGTH_256 [ 0 ] , // [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WDT_DELAY_SEL [ ] = {
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& WDT_DELAY_SEL [ 0 ] , // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SPI_BOOT_CRYPT_CNT [ ] = {
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& SPI_BOOT_CRYPT_CNT [ 0 ] , // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0 [ ] = {
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& SECURE_BOOT_KEY_REVOKE0 [ 0 ] , // [] Revoke 1st secure boot key
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1 [ ] = {
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& SECURE_BOOT_KEY_REVOKE1 [ 0 ] , // [] Revoke 2nd secure boot key
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2 [ ] = {
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& SECURE_BOOT_KEY_REVOKE2 [ 0 ] , // [] Revoke 3rd secure boot key
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY_PURPOSE_0 [ ] = {
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& KEY_PURPOSE_0 [ 0 ] , // [KEY0_PURPOSE] Represents the purpose of Key0
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY_PURPOSE_1 [ ] = {
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& KEY_PURPOSE_1 [ 0 ] , // [KEY1_PURPOSE] Represents the purpose of Key1
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY_PURPOSE_2 [ ] = {
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& KEY_PURPOSE_2 [ 0 ] , // [KEY2_PURPOSE] Represents the purpose of Key2
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY_PURPOSE_3 [ ] = {
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& KEY_PURPOSE_3 [ 0 ] , // [KEY3_PURPOSE] Represents the purpose of Key3
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY_PURPOSE_4 [ ] = {
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& KEY_PURPOSE_4 [ 0 ] , // [KEY4_PURPOSE] Represents the purpose of Key4
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY_PURPOSE_5 [ ] = {
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& KEY_PURPOSE_5 [ 0 ] , // [KEY5_PURPOSE] Represents the purpose of Key5
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SEC_DPA_LEVEL [ ] = {
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& SEC_DPA_LEVEL [ 0 ] , // [] Represents the spa secure level by configuring the clock random divide mode
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_ECDSA_ENABLE_SOFT_K [ ] = {
& ECDSA_ENABLE_SOFT_K [ 0 ] , // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_CRYPT_DPA_ENABLE [ ] = {
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& CRYPT_DPA_ENABLE [ 0 ] , // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_BOOT_EN [ ] = {
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& SECURE_BOOT_EN [ 0 ] , // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE [ ] = {
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& SECURE_BOOT_AGGRESSIVE_REVOKE [ 0 ] , // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FLASH_TYPE [ ] = {
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& FLASH_TYPE [ 0 ] , // [] The type of interfaced flash. 0: four data lines; 1: eight data lines
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FLASH_PAGE_SIZE [ ] = {
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& FLASH_PAGE_SIZE [ 0 ] , // [] Set flash page size
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FLASH_ECC_EN [ ] = {
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& FLASH_ECC_EN [ 0 ] , // [] Set this bit to enable ecc for flash boot
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE [ ] = {
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& DIS_USB_OTG_DOWNLOAD_MODE [ 0 ] , // [] Set this bit to disable download via USB-OTG
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FLASH_TPUW [ ] = {
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& FLASH_TPUW [ 0 ] , // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_DOWNLOAD_MODE [ ] = {
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& DIS_DOWNLOAD_MODE [ 0 ] , // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_DIRECT_BOOT [ ] = {
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& DIS_DIRECT_BOOT [ 0 ] , // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT [ ] = {
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& DIS_USB_SERIAL_JTAG_ROM_PRINT [ 0 ] , // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_LOCK_KM_KEY [ ] = {
& LOCK_KM_KEY [ 0 ] , // [] TBD
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE [ ] = {
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& DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE [ 0 ] , // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD [ ] = {
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& ENABLE_SECURITY_DOWNLOAD [ 0 ] , // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_UART_PRINT_CONTROL [ ] = {
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& UART_PRINT_CONTROL [ 0 ] , // [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_FORCE_SEND_RESUME [ ] = {
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& FORCE_SEND_RESUME [ 0 ] , // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_VERSION [ ] = {
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& SECURE_VERSION [ 0 ] , // [] Represents the version used by ESP-IDF anti-rollback feature
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE [ ] = {
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& SECURE_BOOT_DISABLE_FAST_WAKE [ 0 ] , // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_HYS_EN_PAD [ ] = {
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& HYS_EN_PAD [ 0 ] , // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DCDC_VSET [ ] = {
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& DCDC_VSET [ 0 ] , // [] Set the dcdc voltage default
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_PXA0_TIEH_SEL_0 [ ] = {
& PXA0_TIEH_SEL_0 [ 0 ] , // [] TBD
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_PXA0_TIEH_SEL_1 [ ] = {
& PXA0_TIEH_SEL_1 [ 0 ] , // [] TBD
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_PXA0_TIEH_SEL_2 [ ] = {
& PXA0_TIEH_SEL_2 [ 0 ] , // [] TBD
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_PXA0_TIEH_SEL_3 [ ] = {
& PXA0_TIEH_SEL_3 [ 0 ] , // [] TBD
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_KM_DISABLE_DEPLOY_MODE [ ] = {
& KM_DISABLE_DEPLOY_MODE [ 0 ] , // [] TBD
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_HP_PWR_SRC_SEL [ ] = {
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& HP_PWR_SRC_SEL [ 0 ] , // [] HP system power source select. 0:LDO. 1: DCDC
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DCDC_VSET_EN [ ] = {
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& DCDC_VSET_EN [ 0 ] , // [] Select dcdc vset use efuse_dcdc_vset
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_WDT [ ] = {
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& DIS_WDT [ 0 ] , // [] Set this bit to disable watch dog
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DIS_SWD [ ] = {
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& DIS_SWD [ 0 ] , // [] Set this bit to disable super-watchdog
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_MAC [ ] = {
& MAC [ 0 ] , // [MAC_FACTORY] MAC address
& MAC [ 1 ] , // [MAC_FACTORY] MAC address
& MAC [ 2 ] , // [MAC_FACTORY] MAC address
& MAC [ 3 ] , // [MAC_FACTORY] MAC address
& MAC [ 4 ] , // [MAC_FACTORY] MAC address
& MAC [ 5 ] , // [MAC_FACTORY] MAC address
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_WAFER_VERSION_MINOR [ ] = {
& WAFER_VERSION_MINOR [ 0 ] , // [] Minor chip version
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_WAFER_VERSION_MAJOR [ ] = {
& WAFER_VERSION_MAJOR [ 0 ] , // [] Major chip version
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR [ ] = {
& DISABLE_WAFER_VERSION_MAJOR [ 0 ] , // [] Disables check of wafer version major
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR [ ] = {
& DISABLE_BLK_VERSION_MAJOR [ 0 ] , // [] Disables check of blk version major
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_BLK_VERSION_MINOR [ ] = {
& BLK_VERSION_MINOR [ 0 ] , // [] BLK_VERSION_MINOR of BLOCK2
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_BLK_VERSION_MAJOR [ ] = {
& BLK_VERSION_MAJOR [ 0 ] , // [] BLK_VERSION_MAJOR of BLOCK2
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_PSRAM_CAP [ ] = {
& PSRAM_CAP [ 0 ] , // [] PSRAM capacity
NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_TEMP [ ] = {
& TEMP [ 0 ] , // [] Operating temperature of the ESP chip
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_PSRAM_VENDOR [ ] = {
& PSRAM_VENDOR [ 0 ] , // [] PSRAM vendor
NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_PKG_VERSION [ ] = {
& PKG_VERSION [ 0 ] , // [] Package version
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NULL
} ;
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const esp_efuse_desc_t * ESP_EFUSE_OPTIONAL_UNIQUE_ID [ ] = {
& OPTIONAL_UNIQUE_ID [ 0 ] , // [] Optional unique 128-bit ID
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_USER_DATA [ ] = {
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& USER_DATA [ 0 ] , // [BLOCK_USR_DATA] User data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_USER_DATA_MAC_CUSTOM [ ] = {
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& USER_DATA_MAC_CUSTOM [ 0 ] , // [MAC_CUSTOM CUSTOM_MAC] Custom MAC
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY0 [ ] = {
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& KEY0 [ 0 ] , // [BLOCK_KEY0] Key0 or user data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY1 [ ] = {
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& KEY1 [ 0 ] , // [BLOCK_KEY1] Key1 or user data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY2 [ ] = {
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& KEY2 [ 0 ] , // [BLOCK_KEY2] Key2 or user data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY3 [ ] = {
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& KEY3 [ 0 ] , // [BLOCK_KEY3] Key3 or user data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY4 [ ] = {
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& KEY4 [ 0 ] , // [BLOCK_KEY4] Key4 or user data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_KEY5 [ ] = {
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& KEY5 [ 0 ] , // [BLOCK_KEY5] Key5 or user data
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NULL
} ;
const esp_efuse_desc_t * ESP_EFUSE_SYS_DATA_PART2 [ ] = {
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& SYS_DATA_PART2 [ 0 ] , // [BLOCK_SYS_DATA2] System data part 2 (reserved)
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NULL
} ;