mirror of
https://github.com/espressif/esp-idf.git
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105 lines
2.7 KiB
ArmAsm
105 lines
2.7 KiB
ArmAsm
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.global uxInterruptNesting
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.global uxSchedulerRunning
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.global xIsrStackTop
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.global pxCurrentTCBs
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.global vTaskSwitchContext
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.global xPortSwitchFlag
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.section .text
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/**
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* This function makes the RTOS aware about a ISR entering, it takes the
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* current task stack saved, places into the TCB, loads the ISR stack
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* the interrupted stack must be passed in a0. It needs to receive the
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* ISR nesting code improvements
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*/
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.global rtos_int_enter
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.type rtos_int_enter, @function
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rtos_int_enter:
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/* preserve the return address */
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mv t1, ra
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mv t2, a0
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/* scheduler not enabled, jump directly to ISR handler */
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lw t0, uxSchedulerRunning
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beq t0,zero, rtos_enter_end
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/* increments the ISR nesting count */
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la t3, uxInterruptNesting
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lw t4, 0x0(t3)
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addi t5,t4,1
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sw t5, 0x0(t3)
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/* If reached here from another low-prio ISR, skip stack pushing to TCB */
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bne t4,zero, rtos_enter_end
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/* Save current TCB and load the ISR stack */
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lw t0, pxCurrentTCBs
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sw t2, 0x0(t0)
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lw sp, xIsrStackTop
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rtos_enter_end:
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mv ra, t1
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ret
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/**
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* Recovers the next task to run stack pointer and place it into
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* a0, then the interrupt handler can restore the context of
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* the next task
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*/
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.global rtos_int_exit
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.type rtos_int_exit, @function
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rtos_int_exit:
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/* may skip RTOS aware interrupt since scheduler was not started */
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lw t0, uxSchedulerRunning
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beq t0,zero, rtos_exit_end
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/* update nesting interrupts counter */
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la t2, uxInterruptNesting
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lw t3, 0x0(t2)
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/* Already zero, protect against underflow */
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beq t3, zero, isr_skip_decrement
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addi t3,t3, -1
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sw t3, 0x0(t2)
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isr_skip_decrement:
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/* may still have interrupts pending, skip section below and exit */
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bne t3,zero,rtos_exit_end
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/* Schedule the next task if a yield is pending */
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la t0, xPortSwitchFlag
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lw t2, 0x0(t0)
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beq t2, zero, no_switch
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/* preserve return address and schedule next task
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stack pointer for riscv should always be 16 byte aligned */
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addi sp,sp,-16
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sw ra, 0(sp)
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/* vTaskSwitchContext(xCoreID) now expects xCoreID as an argument, so the assembly calls below have been modified. xCoreID is hard-wired to 0 for single-core risc-v. */
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li a0, 0
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call vTaskSwitchContext
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lw ra, 0(sp)
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addi sp, sp, 16
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/* Clears the switch pending flag */
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la t0, xPortSwitchFlag
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mv t2, zero
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sw t2, 0x0(t0)
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no_switch:
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/* Recover the stack of next task and prepare to exit : */
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lw a0, pxCurrentTCBs
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lw a0, 0x0(a0)
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rtos_exit_end:
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ret
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