2022-04-06 23:59:46 -04:00
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/*
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2023-08-01 05:32:26 -04:00
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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2022-04-06 23:59:46 -04:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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2023-06-28 05:47:19 -04:00
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#include "freertos/idf_additions.h"
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#include "esp_err.h"
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#include "soc/soc_caps.h"
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#include "soc/gdma_channel.h"
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#include "hal/rmt_types.h"
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#include "hal/rmt_hal.h"
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#include "hal/dma_types.h"
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#include "hal/cache_ll.h"
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#include "esp_intr_alloc.h"
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#include "esp_heap_caps.h"
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#include "esp_pm.h"
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#include "esp_attr.h"
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#include "esp_private/gdma.h"
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#include "driver/rmt_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_RMT_ISR_IRAM_SAFE
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#define RMT_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define RMT_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif
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// RMT driver object is per-channel, the interrupt source is shared between channels
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#if CONFIG_RMT_ISR_IRAM_SAFE
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#define RMT_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_IRAM)
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#else
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#define RMT_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED)
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#endif
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// Hopefully the channel offset won't change in other targets
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#define RMT_TX_CHANNEL_OFFSET_IN_GROUP 0
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#define RMT_RX_CHANNEL_OFFSET_IN_GROUP (SOC_RMT_CHANNELS_PER_GROUP - SOC_RMT_TX_CANDIDATES_PER_GROUP)
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#define RMT_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
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// DMA buffer size must align to `rmt_symbol_word_t`
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#define RMT_DMA_DESC_BUF_MAX_SIZE (DMA_DESCRIPTOR_BUFFER_MAX_SIZE & ~(sizeof(rmt_symbol_word_t) - 1))
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#define RMT_DMA_NODES_PING_PONG 2 // two nodes ping-pong
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#define RMT_PM_LOCK_NAME_LEN_MAX 16
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#define RMT_GROUP_INTR_PRIORITY_UNINITIALIZED (-1)
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2023-10-19 03:16:32 -04:00
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// RMT is a slow peripheral, it only supports AHB-GDMA
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#define RMT_DMA_DESC_ALIGN 4
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typedef dma_descriptor_align4_t rmt_dma_descriptor_t;
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#ifdef CACHE_LL_L2MEM_NON_CACHE_ADDR
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#define RMT_GET_NON_CACHE_ADDR(addr) ((addr) ? CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) : 0)
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#else
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#define RMT_GET_NON_CACHE_ADDR(addr) (addr)
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#endif
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typedef struct {
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struct {
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rmt_symbol_word_t symbols[SOC_RMT_MEM_WORDS_PER_CHANNEL];
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} channels[SOC_RMT_CHANNELS_PER_GROUP];
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} rmt_block_mem_t;
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// RMTMEM address is declared in <target>.peripherals.ld
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extern rmt_block_mem_t RMTMEM;
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typedef enum {
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RMT_CHANNEL_DIRECTION_TX,
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RMT_CHANNEL_DIRECTION_RX,
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} rmt_channel_direction_t;
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typedef enum {
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RMT_FSM_INIT,
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RMT_FSM_ENABLE,
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} rmt_fsm_t;
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enum {
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RMT_TX_QUEUE_READY,
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RMT_TX_QUEUE_PROGRESS,
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RMT_TX_QUEUE_COMPLETE,
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RMT_TX_QUEUE_MAX,
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};
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typedef struct rmt_group_t rmt_group_t;
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typedef struct rmt_channel_t rmt_channel_t;
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typedef struct rmt_tx_channel_t rmt_tx_channel_t;
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typedef struct rmt_rx_channel_t rmt_rx_channel_t;
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typedef struct rmt_sync_manager_t rmt_sync_manager_t;
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struct rmt_group_t {
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int group_id; // group ID, index from 0
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portMUX_TYPE spinlock; // to protect per-group register level concurrent access
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rmt_hal_context_t hal; // hal layer for each group
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rmt_clock_source_t clk_src; // record the group clock source, group clock is shared by all channels
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uint32_t resolution_hz; // resolution of group clock
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uint32_t occupy_mask; // a set bit in the mask indicates the channel is not available
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rmt_tx_channel_t *tx_channels[SOC_RMT_TX_CANDIDATES_PER_GROUP]; // array of RMT TX channels
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rmt_rx_channel_t *rx_channels[SOC_RMT_RX_CANDIDATES_PER_GROUP]; // array of RMT RX channels
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rmt_sync_manager_t *sync_manager; // sync manager, this can be extended into an array if there're more sync controllers in one RMT group
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int intr_priority; // RMT interrupt priority
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};
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struct rmt_channel_t {
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int channel_id; // channel ID, index from 0
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int gpio_num; // GPIO number used by RMT RX channel
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uint32_t channel_mask; // mask of the memory blocks that occupied by the channel
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size_t mem_block_num; // number of occupied RMT memory blocks
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rmt_group_t *group; // which group the channel belongs to
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portMUX_TYPE spinlock; // prevent channel resource accessing by user and interrupt concurrently
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uint32_t resolution_hz; // channel clock resolution
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intr_handle_t intr; // allocated interrupt handle for each channel
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rmt_fsm_t fsm; // channel life cycle specific FSM
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rmt_channel_direction_t direction; // channel direction
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rmt_symbol_word_t *hw_mem_base; // base address of RMT channel hardware memory
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rmt_symbol_word_t *dma_mem_base; // base address of RMT channel DMA buffer
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gdma_channel_handle_t dma_chan; // DMA channel
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esp_pm_lock_handle_t pm_lock; // power management lock
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#if CONFIG_PM_ENABLE
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char pm_lock_name[RMT_PM_LOCK_NAME_LEN_MAX]; // pm lock name
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#endif
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// RMT channel common interface
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// The following IO functions will have per-implementation for TX and RX channel
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esp_err_t (*del)(rmt_channel_t *channel);
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esp_err_t (*set_carrier_action)(rmt_channel_t *channel, const rmt_carrier_config_t *config);
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esp_err_t (*enable)(rmt_channel_t *channel);
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esp_err_t (*disable)(rmt_channel_t *channel);
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};
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typedef struct {
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rmt_encoder_handle_t encoder; // encode user payload into RMT symbols
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const void *payload; // encoder payload
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size_t payload_bytes; // payload size
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int loop_count; // transaction can be continued in a loop for specific times
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int remain_loop_count; // user required loop count may exceed hardware limitation, the driver will transfer them in batches
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size_t transmitted_symbol_num; // track the number of transmitted symbols
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struct {
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uint32_t eot_level : 1; // Set the output level for the "End Of Transmission"
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uint32_t encoding_done: 1; // Indicate whether the encoding has finished (not the encoding of transmission)
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} flags;
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} rmt_tx_trans_desc_t;
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struct rmt_tx_channel_t {
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rmt_channel_t base; // channel base class
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size_t mem_off; // runtime argument, indicating the next writing position in the RMT hardware memory
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size_t mem_end; // runtime argument, indicating the end of current writing region
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size_t ping_pong_symbols; // ping-pong size (half of the RMT channel memory)
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size_t queue_size; // size of transaction queue
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size_t num_trans_inflight; // indicates the number of transactions that are undergoing but not recycled to ready_queue
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QueueHandle_t trans_queues[RMT_TX_QUEUE_MAX]; // transaction queues
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rmt_tx_trans_desc_t *cur_trans; // points to current transaction
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void *user_data; // user context
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rmt_tx_done_callback_t on_trans_done; // callback, invoked on trans done
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rmt_dma_descriptor_t *dma_nodes; // DMA descriptor nodes
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rmt_dma_descriptor_t *dma_nodes_nc; // DMA descriptor nodes accessed in non-cached way
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rmt_tx_trans_desc_t trans_desc_pool[]; // transfer descriptor pool
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};
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typedef struct {
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void *buffer; // buffer for saving the received symbols
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size_t buffer_size; // size of the buffer, in bytes
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size_t received_symbol_num; // track the number of received symbols
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size_t copy_dest_off; // tracking offset in the copy destination
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} rmt_rx_trans_desc_t;
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struct rmt_rx_channel_t {
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rmt_channel_t base; // channel base class
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size_t mem_off; // starting offset to fetch the symbols in RMT-MEM
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size_t ping_pong_symbols; // ping-pong size (half of the RMT channel memory)
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rmt_rx_done_callback_t on_recv_done; // callback, invoked on receive done
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void *user_data; // user context
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rmt_rx_trans_desc_t trans_desc; // transaction description
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size_t num_dma_nodes; // number of DMA nodes, determined by how big the memory block that user configures
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rmt_dma_descriptor_t *dma_nodes; // DMA link nodes
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rmt_dma_descriptor_t *dma_nodes_nc; // DMA descriptor nodes accessed in non-cached way
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};
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/**
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* @brief Acquire RMT group handle
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*
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* @param group_id Group ID
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* @return RMT group handle
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*/
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rmt_group_t *rmt_acquire_group_handle(int group_id);
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/**
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* @brief Release RMT group handle
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*
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* @param group RMT group handle, returned from `rmt_acquire_group_handle`
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*/
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void rmt_release_group_handle(rmt_group_t *group);
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/**
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* @brief Set clock source for RMT peripheral
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*
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* @param chan RMT channel handle
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* @param clk_src Clock source
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* @return
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* - ESP_OK: Set clock source successfully
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* - ESP_ERR_NOT_SUPPORTED: Set clock source failed because the clk_src is not supported
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* - ESP_ERR_INVALID_STATE: Set clock source failed because the clk_src is different from other RMT channel
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* - ESP_FAIL: Set clock source failed because of other error
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*/
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esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t clk_src);
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2023-08-29 05:56:03 -04:00
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/**
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* @brief Set interrupt priority to RMT group
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* @param group RMT group to set interrupt priority to
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* @param intr_priority User-specified interrupt priority (in num, not bitmask)
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* @return If the priority conflicts
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* - true: Interrupt priority conflict with previous specified
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* - false: Interrupt priority set successfully
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*/
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bool rmt_set_intr_priority_to_group(rmt_group_t *group, int intr_priority);
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/**
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* @brief Get isr_flags to be passed to `esp_intr_alloc_intrstatus()` according to `intr_priority` set in RMT group
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* @param group RMT group
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* @return isr_flags
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*/
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int rmt_get_isr_flags(rmt_group_t *group);
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#ifdef __cplusplus
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}
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#endif
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