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esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S

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freertos: Add SPDX license identifiers and update xtensa port files This commit does the following: - Adds SPDX license identifiers to FreeRTOS sources. Remove those FreeRTOS sources from the copyright ignore list. - Update xtensa port files to match FreeRTOS v10.4.3. Added SPDX license identifiers to the port files. - Fixed some improperly licensed files - Removed portbenchmark.h from RISC-V port
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/*
feat(freertos): base support on p4
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
freertos: Add SPDX license identifiers and update xtensa port files This commit does the following: - Adds SPDX license identifiers to FreeRTOS sources. Remove those FreeRTOS sources from the copyright ignore list. - Update xtensa port files to match FreeRTOS v10.4.3. Added SPDX license identifiers to the port files. - Fixed some improperly licensed files - Removed portbenchmark.h from RISC-V port
2022-01-29 03:49:56 -05:00
*
* SPDX-License-Identifier: Apache-2.0
*/
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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#include "sdkconfig.h"
#include "portmacro.h"
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
#include "esp_private/hw_stack_guard.h"
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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.global uxInterruptNesting
.global uxSchedulerRunning
.global xIsrStackTop
feat(freertos): base support on p4
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#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7566
.global xIsrStackTop1
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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.global pxCurrentTCB
.global vTaskSwitchContext
.global xPortSwitchFlag
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
.global xIsrStack
.global port_offset_pxStack
.global port_offset_pxEndOfStack
.global esp_hw_stack_guard_monitor_stop
.global esp_hw_stack_guard_monitor_start
.global esp_hw_stack_guard_set_bounds
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
.section .text
/**
* This function makes the RTOS aware about a ISR entering, it takes the
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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* current task stack saved, places into the TCB, loads the ISR stack.
* TODO: ISR nesting code improvements ?
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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*/
.global rtos_int_enter
.type rtos_int_enter, @function
rtos_int_enter:
feat(freertos): base support on p4
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#if CONFIG_IDF_TARGET_ESP32P4
/* needs jira for p4 */
/* preserve the return address */
mv t1, ra
mv t2, a0
#endif
//TODO: IDF-7566
#if !CONFIG_IDF_TARGET_ESP32P4
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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/* scheduler not enabled, jump directly to ISR handler */
esp32c3: format and clean up interrupt and os port code
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lw t0, uxSchedulerRunning
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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beq t0,zero, rtos_enter_end
feat(freertos): base support on p4
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#else
/* scheduler not enabled, jump directly to ISR handler */
csrr t6, mhartid /* t6 = coreID */
slli t6, t6, 2 /* t6 = coreID * 4 */
la t0, uxSchedulerRunning /* t0 = &uxSchedulerRunning */
add t0, t0, t6 /* t0 = &uxSchedulerRunning[coreID] */
lw t0, (t0) /* t0 = uxSchedulerRunning[coreID] */
beq t0,zero, rtos_enter_end
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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/* increments the ISR nesting count */
feat(freertos): base support on p4
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la t3, uxInterruptNesting
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7566
add t3, t3, t6
#endif
lw t4, 0x0(t3)
addi t5,t4,1
sw t5, 0x0(t3)
esp32c3: format and clean up interrupt and os port code
2020-12-28 23:31:54 -05:00
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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/* If reached here from another low-prio ISR, skip stack pushing to TCB */
feat(freertos): base support on p4
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bne t4,zero, rtos_enter_end
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_monitor_stop(); */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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/* Save current TCB and load the ISR stack */
feat(freertos): base support on p4
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//TODO: IDF-7566
#if !CONFIG_IDF_TARGET_ESP32P4
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
lw t0, pxCurrentTCB
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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sw sp, 0x0(t0)
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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lw sp, xIsrStackTop
feat(freertos): base support on p4
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#else
la t0, pxCurrentTCB /* t0 = &pxCurrentTCB */
add t0, t0, t6 /* t0 = &pxCurrentTCB[coreID] */
lw t0, (t0) /* t0 = pxCurrentTCB[coreID] */
sw t2, 0x0(t0)
lw sp, xIsrStackTop
csrr t6, mhartid
beq t6, zero, rtos_enter_end
lw sp, xIsrStackTop1
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
2023-05-04 11:31:31 -04:00
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_set_bounds(xIsrStack, xIsrStackTop); */
la a0, xIsrStack
mv a1, sp
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
ESP_HW_STACK_GUARD_MONITOR_START_CPU0
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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rtos_enter_end:
feat(freertos): base support on p4
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#if CONFIG_IDF_TARGET_ESP32P4
/* needs jira for p4 */
mv ra, t1
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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ret
/**
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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* Recovers the next task to run stack pointer.
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
*/
.global rtos_int_exit
.type rtos_int_exit, @function
rtos_int_exit:
/* may skip RTOS aware interrupt since scheduler was not started */
feat(freertos): base support on p4
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//TODO: IDF-7566
#if !CONFIG_IDF_TARGET_ESP32P4
esp32c3: format and clean up interrupt and os port code
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lw t0, uxSchedulerRunning
feat(freertos): base support on p4
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#else
csrr t1, mhartid
slli t1, t1, 2
la t0, uxSchedulerRunning /* t0 = &uxSchedulerRunning */
add t0, t0, t1 /* t0 = &uxSchedulerRunning[coreID] */
lw t0, (t0)
#endif
esp32c3: format and clean up interrupt and os port code
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beq t0,zero, rtos_exit_end
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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/* update nesting interrupts counter */
freertos: riscv port now uses interrupt allocator and crosscore interrupt
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la t2, uxInterruptNesting
feat(freertos): base support on p4
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#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7566
add t2, t2, t1
#endif
freertos: riscv port now uses interrupt allocator and crosscore interrupt
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lw t3, 0x0(t2)
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available
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/* Already zero, protect against underflow */
freertos: riscv port now uses interrupt allocator and crosscore interrupt
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beq t3, zero, isr_skip_decrement
addi t3,t3, -1
sw t3, 0x0(t2)
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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isr_skip_decrement:
freertos: riscv port now uses interrupt allocator and crosscore interrupt
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/* may still have interrupts pending, skip section below and exit */
esp32c3: format and clean up interrupt and os port code
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bne t3,zero,rtos_exit_end
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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/* Schedule the next task if a yield is pending */
la t0, xPortSwitchFlag
feat(freertos): base support on p4
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#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7566
add t0, t0, t1
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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lw t2, 0x0(t0)
beq t2, zero, no_switch
core: fix cases where riscv SP were not 16 byte aligned RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.
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/* preserve return address and schedule next task
stack pointer for riscv should always be 16 byte aligned */
addi sp,sp,-16
freerots: fix rtos_int_exit writing outside ISR stack rtos_int_exit would store RA at an offset of 4 byte from the SP, where the offset should be 0. This caused rtos_int_exit to overwrite variables in bss.
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sw ra, 0(sp)
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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call vTaskSwitchContext
freerots: fix rtos_int_exit writing outside ISR stack rtos_int_exit would store RA at an offset of 4 byte from the SP, where the offset should be 0. This caused rtos_int_exit to overwrite variables in bss.
2021-01-26 06:05:41 -05:00
lw ra, 0(sp)
core: fix cases where riscv SP were not 16 byte aligned RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.
2021-02-18 22:26:21 -05:00
addi sp, sp, 16
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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/* Clears the switch pending flag */
la t0, xPortSwitchFlag
feat(freertos): base support on p4
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#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7566
/* c routine vTaskSwitchContext may change the temp registers, so we read again */
csrr t3, mhartid
slli t3, t3, 2
add t0, t0, t3
#endif
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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mv t2, zero
sw t2, 0x0(t0)
no_switch:
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
2023-05-04 11:31:31 -04:00
feat(freertos): base support on p4
2023-07-18 04:21:15 -04:00
#if !CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-7566
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_monitor_stop(); */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
/* Recover the stack of next task */
lw t0, pxCurrentTCB
lw sp, 0x0(t0)
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_set_bounds(pxCurrentTCB[0]->pxStack,
* pxCurrentTCB[0]->pxEndOfStack);
*/
lw a0, PORT_OFFSET_PX_STACK(t0)
lw a1, PORT_OFFSET_PX_END_OF_STACK(t0)
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
/* esp_hw_stack_guard_monitor_start(); */
ESP_HW_STACK_GUARD_MONITOR_START_CPU0
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
feat(freertos): base support on p4
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#else
/* Recover the stack of next task and prepare to exit : */
la a0, pxCurrentTCB
/* We may come here from a branch, so we re-cal here */
csrr t3, mhartid
slli t3, t3, 2
add a0, a0, t3 /* a0 = &pxCurrentTCB[coreID] */
lw a0, (a0) /* a0 = pxCurrentTCB[coreID] */
lw a0, 0x0(a0) /* a0 = previous sp */
#endif //#if !CONFIG_IDF_TARGET_ESP32P4
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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rtos_exit_end:
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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ret
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