uint32_tmst_st:4;/*The current status of SPI1 master FSM.*/
uint32_tst:4;/*The current status of SPI1 slave FSM: mspi_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/
uint32_treserved8:9;/*reserved*/
uint32_tflash_pe:1;/*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tusr:1;/*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_hpm:1;/*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_res:1;/*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_dp:1;/*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_ce:1;/*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_be:1;/*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_se:1;/*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_pp:1;/*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_tflash_wrsr:1;/*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_rdsr:1;/*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_rdid:1;/*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_wrdi:1;/*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_wren:1;/*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_read:1;/*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_tval;
}cmd;
uint32_taddr;/*SPI1 address register*/
union{
struct{
uint32_treserved0:3;/*reserved*/
uint32_tfdummy_out:1;/*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_treserved4:3;/*reserved*/
uint32_tfcmd_dual:1;/*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_tfcmd_quad:1;/*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_treserved9:1;/*reserved*/
uint32_tfcs_crc_en:1;/*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_ttx_crc_en:1;/*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_treserved12:1;/*reserved*/
uint32_tfastrd_mode:1;/*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
uint32_twp:1;/*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_twrsr_2b:1;/*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
uint32_tfread_dio:1;/*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_tfread_qio:1;/*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_treserved25:7;/*reserved*/
};
uint32_tval;
}ctrl;
union{
struct{
uint32_tclk_mode:2;/*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_tcs_hold_dly_res:10;/*After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
uint32_trxfifo_wfull_err:1;/*1: SPI0 RX FIFO write full error Cache/EDMA do not read all the data out. 0: Not error.*/
};
uint32_tval;
}ctrl1;
union{
struct{
uint32_tcs_setup_time:5;/*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_tcs_hold_time:5;/*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_treserved10:15;/*reserved*/
uint32_tcs_hold_delay:6;/*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
uint32_tsync_reset:1;/*The FSM will be reset.*/
};
uint32_tval;
}ctrl2;
union{
struct{
uint32_tclkcnt_l:8;/*In the master mode it must be equal to spi_mem_clkcnt_N.*/
uint32_tclkcnt_h:8;/*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_tclkcnt_n:8;/*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_treserved24:7;/*reserved*/
uint32_tclk_equ_sysclk:1;/*Set this bit in 1-division mode.*/
};
uint32_tval;
}clock;
union{
struct{
uint32_treserved0:6;/*reserved*/
uint32_tcs_hold:1;/*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_tcs_setup:1;/*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_treserved8:1;/*reserved*/
uint32_tck_out_edge:1;/*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_treserved10:2;/*reserved*/
uint32_tfwrite_dual:1;/*In the write operations read-data phase apply 2 signals*/
uint32_tfwrite_quad:1;/*In the write operations read-data phase apply 4 signals*/
uint32_tfwrite_dio:1;/*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_tfwrite_qio:1;/*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_treserved16:8;/*reserved*/
uint32_tusr_miso_highpart:1;/*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_tusr_mosi_highpart:1;/*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_tusr_dummy_idle:1;/*SPI clock is disable in dummy phase when the bit is enable.*/
uint32_tusr_mosi:1;/*This bit enable the write-data phase of an operation.*/
uint32_tusr_miso:1;/*This bit enable the read-data phase of an operation.*/
uint32_tusr_dummy:1;/*This bit enable the dummy phase of an operation.*/
uint32_tusr_addr:1;/*This bit enable the address phase of an operation.*/
uint32_tusr_command:1;/*This bit enable the command phase of an operation.*/
};
uint32_tval;
}user;
union{
struct{
uint32_tusr_dummy_cyclelen:6;/*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_treserved6:20;/*reserved*/
uint32_tusr_addr_bitlen:6;/*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_tval;
}user1;
union{
struct{
uint32_tusr_command_value:16;/*The value of command.*/
uint32_treserved16:12;/*reserved*/
uint32_tusr_command_bitlen:4;/*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_tval;
}user2;
union{
struct{
uint32_tusr_mosi_bit_len:10;/*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_treserved10:22;/*reserved*/
};
uint32_tval;
}mosi_dlen;
union{
struct{
uint32_tusr_miso_bit_len:10;/*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_treserved10:22;/*reserved*/
};
uint32_tval;
}miso_dlen;
union{
struct{
uint32_tstatus:16;/*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
uint32_twb_mode:8;/*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_treserved24:8;/*reserved*/
};
uint32_tval;
}rd_status;
uint32_treserved_30;
union{
struct{
uint32_tcs0_dis:1;/*SPI_CS0 pin enable 1: disable SPI_CS0 0: SPI_CS0 pin is active to select SPI device such as flash external RAM and so on.*/
uint32_tcs1_dis:1;/*SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active to select SPI device such as flash external RAM and so on.*/
uint32_treserved2:1;/*reserved*/
uint32_tmst_st_trans_end:1;/*The bit is used to indicate the spi0_mst_st controlled transmitting is done.*/
uint32_tmst_st_trans_end_en:1;/*The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.*/
uint32_tst_trans_end:1;/*The bit is used to indicate the spi0_slv_st controlled transmitting is done.*/
uint32_tst_trans_end_en:1;/*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
uint32_treserved7:2;/*reserved*/
uint32_tck_idle_edge:1;/*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_tcs_keep_active:1;/*spi cs line keep low when the bit is set.*/
uint32_tflash_usr_cmd:1;/*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
uint32_tfdin_dual:1;/*For SPI1 din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_tfdout_dual:1;/*For SPI1 dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_tfaddr_dual:1;/*For SPI1 address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_tfdin_quad:1;/*For SPI1 din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_tfdout_quad:1;/*For SPI1 dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_tfaddr_quad:1;/*For SPI1 address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_treserved9:23;/*reserved*/
};
uint32_tval;
}cache_fctrl;
uint32_treserved_40;
uint32_treserved_44;
uint32_treserved_48;
uint32_treserved_4c;
uint32_treserved_50;
union{
struct{
uint32_tspi0_st:4;/*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/
uint32_tspi0_mst_st:3;/*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state 1:EM_CACHE_GRANT 2: program/erase suspend state 3: SPI0 read data state 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO 5: SPI0 write data state.*/
uint32_tcspi_lock_delay_time:5;/*The lock delay time of SPI0/1 arbiter by spi0_slv_st after PER is sent by SPI1.*/
uint32_treserved12:20;/*reserved*/
};
uint32_tval;
}fsm;
uint32_tdata_buf[16];
union{
struct{
uint32_treserved0:1;/*reserved*/
uint32_twaiti_dummy:1;/*The dummy phase enable when wait flash idle (RDSR)*/
uint32_twaiti_cmd:8;/*The command to wait flash idle(RDSR).*/
uint32_twaiti_dummy_cyclelen:6;/*The dummy cycle length when wait flash idle(RDSR).*/
uint32_treserved16:16;/*reserved*/
};
uint32_tval;
}flash_waiti_ctrl;
union{
struct{
uint32_tflash_per:1;/*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_pes:1;/*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_per_wait_en:1;/*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/
uint32_tflash_pes_wait_en:1;/*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/
uint32_tpes_per_en:1;/*Set this bit to enable PES end triggers PER transfer option. If this bit is 0 application should send PER after PES is done.*/
uint32_tflash_pes_en:1;/*Set this bit to enable Auto-suspending function.*/
uint32_tpesr_end_msk:16;/*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out status_in[15:0] is valid when two bytes of data are read out) SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
uint32_tfrd_sus_2b:1;/*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/
uint32_tper_end_en:1;/*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
uint32_tpes_end_en:1;/*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
uint32_tsus_timeout_cnt:7;/*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times it will be treated as check pass.*/
uint32_twait_pesr_command:16;/*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
};
uint32_tval;
}flash_sus_cmd;
union{
struct{
uint32_tflash_sus:1;/*The status of flash suspend only used in SPI1.*/
uint32_treserved1:31;/*reserved*/
};
uint32_tval;
}sus_status;
union{
struct{
uint32_ttiming_clk_ena:1;/*The bit is used to enable timing adjust clock for all reading operations.*/
uint32_ttiming_cali:1;/*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_textra_dummy_cyclelen:3;/*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_treserved5:27;/*reserved*/
};
uint32_tval;
}timing_cali;
union{
struct{
uint32_tdin0_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin1_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin2_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin3_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_treserved8:24;/*reserved*/
};
uint32_tval;
}din_mode;
union{
struct{
uint32_tdin0_num:2;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tdin1_num:2;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tdin2_num:2;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tdin3_num:2;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_treserved8:24;/*reserved*/
};
uint32_tval;
}din_num;
union{
struct{
uint32_tdout0_mode:1;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout1_mode:1;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout2_mode:1;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout3_mode:1;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_treserved4:28;/*reserved*/
};
uint32_tval;
}dout_mode;
uint32_treserved_b8;
uint32_treserved_bc;
union{
struct{
uint32_tper_end_int_ena:1;/*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_tpes_end_int_ena:1;/*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_twpe_end_int_ena:1;/*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_tst_end_int_ena:1;/*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_tmst_st_end_int_ena:1;/*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_treserved5:27;/*reserved*/
};
uint32_tval;
}int_ena;
union{
struct{
uint32_tper_end:1;/*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_tpes_end:1;/*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_twpe_end:1;/*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_tst_end:1;/*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_tmst_st_end:1;/*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_treserved5:27;/*reserved*/
};
uint32_tval;
}int_clr;
union{
struct{
uint32_tper_end:1;/*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
uint32_tpes_end:1;/*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
uint32_twpe_end:1;/*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
uint32_tst_end:1;/*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
uint32_tmst_st_end:1;/*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
uint32_treserved5:27;/*reserved*/
};
uint32_tval;
}int_raw;
union{
struct{
uint32_tper_end:1;/*The status bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_tpes_end:1;/*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_twpe_end:1;/*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_tst_end:1;/*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_tmst_st_end:1;/*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_tspi01_clk_sel:2;/*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
