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72 lines
2.4 KiB
Markdown
72 lines
2.4 KiB
Markdown
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| Supported Targets | ESP32-S2 | ESP32-S3 |
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| ----------------- | -------- | -------- |
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# ULP-RISC-V Interrupt Handling:
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This example demonstrates how the ULP-RISC-V coprocessor can register and handle interrupts. Currently this example supports handling of -
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- Software triggered interrupts
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- RTC IO triggered interrupts
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The example keeps a count of the software interrupts triggered on the ULP RISC-V core and wakes up the main processor from deep sleep after a certain threshold.
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Additionaly, it wakes up the main processor from deep sleep when a button is pressed and the GPIO interrupt is triggered.
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## How to use example
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### Hardware Required
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The example can be run on any ESP32-S2 or ESP32-S3 based development board connected to a computer with a single USB cable for flashing and monitoring. The external interface should have 3.3V outputs. You may use e.g. 3.3V compatible USB-to-Serial dongle.
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### Build and Flash
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Build the project and flash it to the board, then run monitor tool to view serial output:
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```
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idf.py -p PORT flash monitor
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```
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(To exit the serial monitor, type ``Ctrl-]``.)
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By default, this example uses GPIO#0 which is connected to the "Boot" button on esp32-s2/s3 development boards. To trigger the GPIO interrupt on the ULP RISC-V core, press the Boot button.
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## Example Output
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Output from main CPU:
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```
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Not a ULP RISC-V wakeup, initializing it!
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Entering in deep sleep
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ESP-ROM:esp32s3-20210327
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Build:Mar 27 2021
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rst:0x5 (DSLEEP),boot:0x8 (SPI_FAST_FLASH_BOOT)
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pro cpu reset by JTAG
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SPIWP:0xee
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mode:DIO, clock div:1
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load:0x3fce3810,len:0x12b4
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load:0x403c9700,len:0x4
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load:0x403c9704,len:0xaf4
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load:0x403cc700,len:0x2bcc
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entry 0x403c9898
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W (91) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
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ULP RISC-V woke up the main CPU!
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ULP RISC-V SW Interrupt triggered 5 times.
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Entering in deep sleep
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ESP-ROM:esp32s3-20210327
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Build:Mar 27 2021
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rst:0x5 (DSLEEP),boot:0x8 (SPI_FAST_FLASH_BOOT)
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pro cpu reset by JTAG
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SPIWP:0xee
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mode:DIO, clock div:1
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load:0x3fce3810,len:0x12b4
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load:0x403c9700,len:0x4
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load:0x403c9704,len:0xaf4
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load:0x403cc700,len:0x2bcc
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entry 0x403c9898
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W (91) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
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ULP RISC-V woke up the main CPU!
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ULP RISC-V GPIO Interrupt triggered.
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Entering in deep sleep
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```
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