2022-04-07 05:37:33 -04:00
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-10-10 00:35:13 -04:00
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// The HAL layer for SDIO slave (common part)
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#include <string.h>
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2021-05-18 22:53:21 -04:00
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#include "soc/slc_struct.h"
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#include "soc/hinf_struct.h"
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#include "hal/sdio_slave_types.h"
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#include "soc/host_struct.h"
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2019-10-10 00:35:13 -04:00
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#include "hal/sdio_slave_hal.h"
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2021-05-18 22:53:21 -04:00
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#include "hal/assert.h"
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#include "hal/log.h"
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2019-10-10 00:35:13 -04:00
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#include "esp_attr.h"
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#define SDIO_SLAVE_CHECK(res, str, ret_val) do { if(!(res)){\
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HAL_LOGE(TAG, "%s", str);\
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return ret_val;\
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} }while (0)
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2022-04-07 05:37:33 -04:00
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/* The tag may be unused if log level is set to NONE */
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static const __attribute__((unused)) char TAG[] = "SDIO_HAL";
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2019-10-10 00:35:13 -04:00
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static esp_err_t init_send_queue(sdio_slave_context_t *hal);
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/**************** Ring buffer for SDIO sending use *****************/
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typedef enum {
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RINGBUF_GET_ONE = 0,
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RINGBUF_GET_ALL = 1,
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} ringbuf_get_all_t;
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typedef enum {
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RINGBUF_WRITE_PTR,
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RINGBUF_READ_PTR,
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RINGBUF_FREE_PTR,
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} sdio_ringbuf_pointer_t;
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static esp_err_t sdio_ringbuf_send(sdio_ringbuf_t *buf, esp_err_t (*copy_callback)(uint8_t *, void *), void *arg);
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2023-01-18 12:04:06 -05:00
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static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all);
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2019-10-10 00:35:13 -04:00
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static inline int sdio_ringbuf_return(sdio_ringbuf_t* buf, uint8_t *ptr);
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#define _SEND_DESC_NEXT(x) STAILQ_NEXT(&((sdio_slave_hal_send_desc_t*)x)->dma_desc, qe)
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#define SEND_DESC_NEXT(x) (sdio_slave_hal_send_desc_t*)_SEND_DESC_NEXT(x)
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#define SEND_DESC_NEXT_SET(x, target) do { \
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_SEND_DESC_NEXT(x)=(lldesc_t*)target; \
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}while(0)
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static esp_err_t link_desc_to_last(uint8_t* desc, void* arg)
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{
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SEND_DESC_NEXT_SET(arg, desc);
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return ESP_OK;
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}
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//calculate a pointer with offset to a original pointer of the specific ringbuffer
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static inline uint8_t* sdio_ringbuf_offset_ptr(sdio_ringbuf_t *buf, sdio_ringbuf_pointer_t ptr, uint32_t offset)
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{
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uint8_t *buf_ptr;
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switch (ptr) {
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case RINGBUF_WRITE_PTR:
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buf_ptr = buf->write_ptr;
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break;
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case RINGBUF_READ_PTR:
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buf_ptr = buf->read_ptr;
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break;
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case RINGBUF_FREE_PTR:
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buf_ptr = buf->free_ptr;
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break;
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default:
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abort();
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}
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uint8_t *offset_ptr=buf_ptr+offset;
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if (offset_ptr >= buf->data + buf->size) {
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offset_ptr -= buf->size;
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}
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return offset_ptr;
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}
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static esp_err_t sdio_ringbuf_send(sdio_ringbuf_t *buf, esp_err_t (*copy_callback)(uint8_t *, void *), void *arg)
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{
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uint8_t* get_ptr = sdio_ringbuf_offset_ptr(buf, RINGBUF_WRITE_PTR, SDIO_SLAVE_SEND_DESC_SIZE);
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esp_err_t err = ESP_OK;
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if (copy_callback) {
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2021-03-23 11:09:53 -04:00
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err = (*copy_callback)(get_ptr, arg);
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2019-10-10 00:35:13 -04:00
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}
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if (err != ESP_OK) return err;
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buf->write_ptr = get_ptr;
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return ESP_OK;
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}
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// this ringbuf is a return-before-recv-again strategy
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// since this is designed to be called in the ISR, no parallel logic
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2023-01-18 12:04:06 -05:00
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static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all)
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2019-10-10 00:35:13 -04:00
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{
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2021-05-18 22:53:21 -04:00
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HAL_ASSERT(buf->free_ptr == buf->read_ptr); //must return before recv again
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2019-10-10 00:35:13 -04:00
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if (start == NULL && end == NULL) return ESP_ERR_INVALID_ARG; // must have a output
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if (buf->read_ptr == buf->write_ptr) return ESP_ERR_NOT_FOUND; // no data
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uint8_t *get_start = sdio_ringbuf_offset_ptr(buf, RINGBUF_READ_PTR, SDIO_SLAVE_SEND_DESC_SIZE);
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if (get_all != RINGBUF_GET_ONE) {
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buf->read_ptr = buf->write_ptr;
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} else {
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buf->read_ptr = get_start;
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}
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if (start != NULL) {
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*start = get_start;
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}
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if (end != NULL) {
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*end = buf->read_ptr;
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}
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return ESP_OK;
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}
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static inline int sdio_ringbuf_return(sdio_ringbuf_t* buf, uint8_t *ptr)
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{
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2021-05-18 22:53:21 -04:00
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HAL_ASSERT(sdio_ringbuf_offset_ptr(buf, RINGBUF_FREE_PTR, SDIO_SLAVE_SEND_DESC_SIZE) == ptr);
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2020-11-16 23:48:35 -05:00
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size_t size = (buf->read_ptr + buf->size - buf->free_ptr) % buf->size;
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size_t count = size / SDIO_SLAVE_SEND_DESC_SIZE;
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2021-05-18 22:53:21 -04:00
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HAL_ASSERT(count * SDIO_SLAVE_SEND_DESC_SIZE==size);
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2019-10-10 00:35:13 -04:00
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buf->free_ptr = buf->read_ptr;
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return count;
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}
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static inline uint8_t* sdio_ringbuf_peek_front(sdio_ringbuf_t* buf)
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{
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if (buf->read_ptr != buf->write_ptr) {
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return sdio_ringbuf_offset_ptr(buf, RINGBUF_READ_PTR, SDIO_SLAVE_SEND_DESC_SIZE);
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} else {
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return NULL;
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}
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}
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static inline uint8_t* sdio_ringbuf_peek_rear(sdio_ringbuf_t *buf)
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{
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return buf->write_ptr;
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}
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static inline bool sdio_ringbuf_empty(sdio_ringbuf_t* buf)
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{
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return (buf->read_ptr == buf->write_ptr);
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}
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/**************** End of Ring buffer *****************/
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void sdio_slave_hal_init(sdio_slave_context_t *hal)
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{
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hal->host = sdio_slave_ll_get_host(0);
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hal->slc = sdio_slave_ll_get_slc(0);
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hal->hinf = sdio_slave_ll_get_hinf(0);
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hal->send_state = STATE_IDLE;
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hal->recv_link_list = (sdio_slave_hal_recv_stailq_t)STAILQ_HEAD_INITIALIZER(hal->recv_link_list);
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init_send_queue(hal);
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}
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void sdio_slave_hal_hw_init(sdio_slave_context_t *hal)
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{
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sdio_slave_ll_init(hal->slc);
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2022-09-23 03:51:43 -04:00
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sdio_slave_ll_enable_hs(hal->hinf, !hal->no_highspeed);
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2019-10-10 00:35:13 -04:00
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sdio_slave_ll_set_timing(hal->host, hal->timing);
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sdio_slave_ll_slvint_t intr_ena = 0xff;
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sdio_slave_ll_slvint_set_ena(hal->slc, &intr_ena);
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}
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static esp_err_t init_send_queue(sdio_slave_context_t *hal)
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{
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esp_err_t ret;
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2021-02-12 00:01:05 -05:00
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esp_err_t rcv_res __attribute((unused));
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2019-10-10 00:35:13 -04:00
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sdio_ringbuf_t *buf = &(hal->send_desc_queue);
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//initialize pointers
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buf->write_ptr = buf->data;
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buf->read_ptr = buf->data;
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buf->free_ptr = buf->data;
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sdio_slave_hal_send_desc_t *first = NULL, *last = NULL;
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//no copy for the first descriptor
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ret = sdio_ringbuf_send(buf, NULL, NULL);
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if (ret != ESP_OK) return ret;
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//loop in the ringbuf to link all the desc one after another as a ring
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for (int i = 0; i < hal->send_queue_size + 1; i++) {
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rcv_res = sdio_ringbuf_recv(buf, (uint8_t **) &last, NULL, RINGBUF_GET_ONE);
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assert (rcv_res == ESP_OK);
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ret = sdio_ringbuf_send(buf, link_desc_to_last, last);
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if (ret != ESP_OK) return ret;
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sdio_ringbuf_return(buf, (uint8_t *) last);
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}
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first = NULL;
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last = NULL;
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//clear the queue
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rcv_res = sdio_ringbuf_recv(buf, (uint8_t **) &first, (uint8_t **) &last, RINGBUF_GET_ALL);
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assert (rcv_res == ESP_OK);
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2021-05-18 22:53:21 -04:00
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HAL_ASSERT(first == last); //there should be only one desc remain
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2019-10-10 00:35:13 -04:00
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sdio_ringbuf_return(buf, (uint8_t *) first);
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return ESP_OK;
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}
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void sdio_slave_hal_set_ioready(sdio_slave_context_t *hal, bool ready)
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{
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sdio_slave_ll_set_ioready(hal->hinf, ready); //set IO ready to 1 to allow host to use
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}
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/*---------------------------------------------------------------------------
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* Send
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*
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* The hardware has a cache, so that once a descriptor is loaded onto the linked-list, it cannot be modified
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* until returned (used) by the hardware. This forbids us from loading descriptors onto the linked list during
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* the transfer (or the time waiting for host to start a transfer). However, we use a "ringbuffer" (different from
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* the one in ``freertos/`` folder) holding descriptors to solve this:
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* 1. The driver allocates continuous memory for several buffer descriptors (the maximum buffer number) during
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* initialization. Then the driver points the STAILQ_NEXT pointer of all the descriptors except the last one
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* to the next descriptor of each of them. Then the pointer of the last descriptor points back to the first one:
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* now the descriptor is in a ring.
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* 2. The "ringbuffer" has a write pointer points to where app can write new descriptor. The app writes the new descriptor
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* indicated by the write pointer without touching the STAILQ_NEXT pointer so that the descriptors are always in a
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* ring-like linked-list. The app never touches the part of linked-list being used by the hardware.
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* 3. When the hardware needs some data to send, it automatically pick a part of linked descriptors. According to the mode:
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* - Buffer mode: only pick the next one to the last one sent;
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* - Stream mode: pick the whole unsent linked list, starting from the one above, to the latest linked one.
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* The driver removes the STAILQ_NEXT pointer of the last descriptor and put the head of the part to the DMA controller so
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* that it looks like just a linear linked-list rather than a ring to the hardware.
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* 4. The counter of sending FIFO can increase when app load new buffers (in STREAM_MODE) or when new transfer should
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* start (in PACKET_MODE).
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* 5. When the sending transfer is finished, the driver goes through the descriptors just send in the ISR and push all
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* the ``arg`` member of descriptors to the queue back to the app, so that the app can handle finished buffers. The
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* driver also fix the STAILQ_NEXT pointer of the last descriptor so that the descriptors are now in a ring again.
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----------------------------------------------------------------------------*/
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static inline void send_set_state(sdio_slave_context_t *hal, send_state_t state)
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{
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hal->send_state = state;
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}
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static inline send_state_t send_get_state(sdio_slave_context_t* hal)
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{
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return hal->send_state;
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}
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DMA_ATTR static const lldesc_t start_desc = {
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.owner = 1,
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.buf = (void*)0x3ffbbbbb, //assign a dma-capable pointer other than NULL, which will not be used
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.size = 1,
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.length = 1,
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.eof = 1,
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};
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//force trigger rx_done interrupt. the interrupt is abused to invoke ISR from the app by the enable bit and never cleared.
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static void send_isr_invoker_enable(const sdio_slave_context_t *hal)
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{
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sdio_slave_ll_send_reset(hal->slc);
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sdio_slave_ll_send_start(hal->slc, &start_desc);
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//wait for rx_done
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while(!sdio_slave_ll_send_invoker_ready(hal->slc));
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sdio_slave_ll_send_stop(hal->slc);
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sdio_slave_ll_send_hostint_clr(hal->host);
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}
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static void send_isr_invoker_disable(sdio_slave_context_t *hal)
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{
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sdio_slave_ll_send_part_done_clear(hal->slc);
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}
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void sdio_slave_hal_send_handle_isr_invoke(sdio_slave_context_t *hal)
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{
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sdio_slave_ll_send_part_done_intr_ena(hal->slc, false);
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}
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//start hw operation with existing data (if exist)
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esp_err_t sdio_slave_hal_send_start(sdio_slave_context_t *hal)
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{
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SDIO_SLAVE_CHECK(send_get_state(hal) == STATE_IDLE,
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"already started", ESP_ERR_INVALID_STATE);
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send_set_state(hal, STATE_WAIT_FOR_START);
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send_isr_invoker_enable(hal);
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sdio_slave_ll_send_intr_clr(hal->slc);
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sdio_slave_ll_send_intr_ena(hal->slc, true);
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return ESP_OK;
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}
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//only stop hw operations, no touch to data as well as counter
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void sdio_slave_hal_send_stop(sdio_slave_context_t *hal)
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{
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sdio_slave_ll_send_stop(hal->slc);
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send_isr_invoker_disable(hal);
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sdio_slave_ll_send_intr_ena(hal->slc, false);
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send_set_state(hal, STATE_IDLE);
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}
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static void send_new_packet(sdio_slave_context_t *hal)
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{
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// since eof is changed, we have to stop and reset the link list,
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// and restart new link list operation
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sdio_slave_hal_send_desc_t *const start_desc = hal->in_flight_head;
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sdio_slave_hal_send_desc_t *const end_desc = hal->in_flight_end;
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(start_desc != NULL && end_desc != NULL);
|
2019-10-10 00:35:13 -04:00
|
|
|
|
|
|
|
sdio_slave_ll_send_stop(hal->slc);
|
|
|
|
sdio_slave_ll_send_reset(hal->slc);
|
|
|
|
sdio_slave_ll_send_start(hal->slc, (lldesc_t*)start_desc);
|
|
|
|
|
|
|
|
// update pkt_len register to allow host reading.
|
|
|
|
sdio_slave_ll_send_write_len(hal->slc, end_desc->pkt_len);
|
2021-09-01 01:58:47 -04:00
|
|
|
HAL_EARLY_LOGV(TAG, "send_length_write: %d, last_len: %08X", end_desc->pkt_len, sdio_slave_ll_send_read_len(hal->host));
|
2019-10-10 00:35:13 -04:00
|
|
|
|
|
|
|
send_set_state(hal, STATE_SENDING);
|
|
|
|
|
2021-09-01 01:58:47 -04:00
|
|
|
HAL_EARLY_LOGD(TAG, "restart new send: %p->%p, pkt_len: %d", start_desc, end_desc, end_desc->pkt_len);
|
2019-10-10 00:35:13 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t send_check_new_packet(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
esp_err_t ret;
|
|
|
|
sdio_slave_hal_send_desc_t *start = NULL;
|
|
|
|
sdio_slave_hal_send_desc_t *end = NULL;
|
|
|
|
if (hal->sending_mode == SDIO_SLAVE_SEND_PACKET) {
|
|
|
|
ret = sdio_ringbuf_recv(&(hal->send_desc_queue), (uint8_t **) &start, (uint8_t **) &end, RINGBUF_GET_ONE);
|
|
|
|
} else { //stream mode
|
|
|
|
ret = sdio_ringbuf_recv(&(hal->send_desc_queue), (uint8_t **) &start, (uint8_t **) &end, RINGBUF_GET_ALL);
|
|
|
|
}
|
|
|
|
if (ret == ESP_OK) {
|
|
|
|
hal->in_flight_head = start;
|
|
|
|
hal->in_flight_end = end;
|
|
|
|
end->dma_desc.eof = 1;
|
|
|
|
//temporarily break the link ring here, the ring will be re-connected in ``send_isr_eof()``.
|
|
|
|
hal->in_flight_next = SEND_DESC_NEXT(end);
|
|
|
|
SEND_DESC_NEXT_SET(end, NULL);
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool sdio_slave_hal_send_eof_happened(sdio_slave_context_t* hal)
|
|
|
|
{
|
|
|
|
// Goto idle state (cur_start=NULL) if transmission done,
|
|
|
|
// also update sequence and recycle descs.
|
|
|
|
if (sdio_slave_ll_send_done(hal->slc)) {
|
|
|
|
//check current state
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(send_get_state(hal) == STATE_SENDING);
|
2019-10-10 00:35:13 -04:00
|
|
|
sdio_slave_ll_send_intr_clr(hal->slc);
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
//clear counter but keep data
|
|
|
|
esp_err_t sdio_slave_hal_send_reset_counter(sdio_slave_context_t* hal)
|
|
|
|
{
|
|
|
|
SDIO_SLAVE_CHECK(send_get_state(hal) == STATE_IDLE,
|
|
|
|
"reset counter when transmission started", ESP_ERR_INVALID_STATE);
|
|
|
|
|
|
|
|
sdio_slave_ll_send_write_len(hal->slc, 0);
|
2021-09-01 01:58:47 -04:00
|
|
|
HAL_EARLY_LOGV(TAG, "last_len: %08X", sdio_slave_ll_send_read_len(hal->host));
|
2019-10-10 00:35:13 -04:00
|
|
|
|
|
|
|
hal->tail_pkt_len = 0;
|
|
|
|
sdio_slave_hal_send_desc_t *desc = hal->in_flight_head;
|
|
|
|
while(desc != NULL) {
|
|
|
|
hal->tail_pkt_len += desc->dma_desc.length;
|
|
|
|
desc->pkt_len = hal->tail_pkt_len;
|
|
|
|
desc = SEND_DESC_NEXT(desc);
|
|
|
|
}
|
|
|
|
// in theory the desc should be the one right next to the last of in_flight_head,
|
|
|
|
// but the link of last is NULL, so get the desc from the ringbuf directly.
|
|
|
|
desc = (sdio_slave_hal_send_desc_t*)sdio_ringbuf_peek_front(&(hal->send_desc_queue));
|
|
|
|
while(desc != NULL) {
|
|
|
|
hal->tail_pkt_len += desc->dma_desc.length;
|
|
|
|
desc->pkt_len = hal->tail_pkt_len;
|
|
|
|
desc = SEND_DESC_NEXT(desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t send_get_inflight_desc(sdio_slave_context_t *hal, void **out_arg, uint32_t *out_returned_cnt,
|
|
|
|
bool init)
|
|
|
|
{
|
|
|
|
esp_err_t ret;
|
|
|
|
if (init) {
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(hal->returned_desc == NULL);
|
2019-10-10 00:35:13 -04:00
|
|
|
hal->returned_desc = hal->in_flight_head;
|
|
|
|
send_set_state(hal, STATE_GETTING_RESULT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hal->returned_desc != NULL) {
|
|
|
|
*out_arg = hal->returned_desc->arg;
|
|
|
|
hal->returned_desc = SEND_DESC_NEXT(hal->returned_desc);
|
|
|
|
ret = ESP_OK;
|
|
|
|
} else {
|
|
|
|
if (hal->in_flight_head != NULL) {
|
|
|
|
// fix the link broken of last desc when being sent
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(hal->in_flight_end != NULL);
|
2019-10-10 00:35:13 -04:00
|
|
|
SEND_DESC_NEXT_SET(hal->in_flight_end, hal->in_flight_next);
|
|
|
|
|
|
|
|
*out_returned_cnt = sdio_ringbuf_return(&(hal->send_desc_queue), (uint8_t*)hal->in_flight_head);
|
|
|
|
}
|
|
|
|
|
|
|
|
hal->in_flight_head = NULL;
|
|
|
|
hal->in_flight_end = NULL;
|
|
|
|
|
|
|
|
ret = ESP_ERR_NOT_FOUND;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t send_get_unsent_desc(sdio_slave_context_t *hal, void **out_arg, uint32_t *out_return_cnt)
|
|
|
|
{
|
|
|
|
esp_err_t ret;
|
2022-02-22 07:19:45 -05:00
|
|
|
sdio_slave_hal_send_desc_t *head = NULL;
|
|
|
|
sdio_slave_hal_send_desc_t *tail = NULL;
|
2019-10-10 00:35:13 -04:00
|
|
|
ret = sdio_ringbuf_recv(&(hal->send_desc_queue), (uint8_t **) &head, (uint8_t **) &tail, RINGBUF_GET_ONE);
|
|
|
|
|
|
|
|
if (ret == ESP_OK) {
|
|
|
|
//currently each packet takes only one desc.
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(head == tail);
|
2019-10-10 00:35:13 -04:00
|
|
|
(*out_arg) = head->arg;
|
|
|
|
(*out_return_cnt) = sdio_ringbuf_return(&(hal->send_desc_queue), (uint8_t*) head);
|
|
|
|
} else if (ret == ESP_ERR_NOT_FOUND) {
|
|
|
|
// if in wait to send state, set the sequence number of tail to the value last sent, just as if the packet wait to
|
|
|
|
// send never queued.
|
|
|
|
// Go to idle state (cur_end!=NULL and cur_start=NULL)
|
|
|
|
send_set_state(hal, STATE_IDLE);
|
|
|
|
hal->tail_pkt_len = sdio_slave_ll_send_read_len(hal->host);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t sdio_slave_hal_send_get_next_finished_arg(sdio_slave_context_t *hal, void **out_arg, uint32_t* out_returned_cnt)
|
|
|
|
{
|
|
|
|
bool init = (send_get_state(hal) == STATE_SENDING);
|
|
|
|
if (init) {
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(hal->in_flight_head != NULL);
|
2019-10-10 00:35:13 -04:00
|
|
|
} else {
|
2021-05-18 22:53:21 -04:00
|
|
|
HAL_ASSERT(send_get_state(hal) == STATE_GETTING_RESULT);
|
2019-10-10 00:35:13 -04:00
|
|
|
}
|
|
|
|
*out_returned_cnt = 0;
|
|
|
|
|
|
|
|
esp_err_t ret = send_get_inflight_desc(hal, out_arg, out_returned_cnt, init);
|
|
|
|
|
|
|
|
if (ret == ESP_ERR_NOT_FOUND) {
|
|
|
|
// Go to wait for packet state
|
|
|
|
send_set_state(hal, STATE_WAIT_FOR_START);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
esp_err_t sdio_slave_hal_send_flush_next_buffer(sdio_slave_context_t *hal, void **out_arg, uint32_t *out_return_cnt)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
*out_return_cnt = 0;
|
|
|
|
bool init = (send_get_state(hal) == STATE_IDLE);
|
|
|
|
if (!init) {
|
|
|
|
if (send_get_state(hal) != STATE_GETTING_RESULT && send_get_state(hal) != STATE_GETTING_UNSENT_DESC) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (init || send_get_state(hal) == STATE_GETTING_RESULT) {
|
|
|
|
ret = send_get_inflight_desc(hal, out_arg, out_return_cnt, init);
|
|
|
|
if (ret == ESP_ERR_NOT_FOUND) {
|
|
|
|
send_set_state(hal, STATE_GETTING_UNSENT_DESC);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (send_get_state(hal) == STATE_GETTING_UNSENT_DESC) {
|
|
|
|
ret = send_get_unsent_desc(hal, out_arg, out_return_cnt);
|
|
|
|
if (ret == ESP_ERR_NOT_FOUND) {
|
|
|
|
send_set_state(hal, STATE_IDLE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t sdio_slave_hal_send_new_packet_if_exist(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
esp_err_t ret;
|
|
|
|
// Go to wait sending state (cur_start!=NULL && cur_end==NULL) if not sending and new packet ready.
|
|
|
|
// Note we may also enter this state by stopping sending in the app.
|
|
|
|
if (send_get_state(hal) == STATE_WAIT_FOR_START) {
|
|
|
|
if (hal->in_flight_head == NULL) {
|
|
|
|
send_check_new_packet(hal);
|
|
|
|
}
|
|
|
|
// Go to sending state (cur_start and cur_end != NULL) if has packet to send.
|
|
|
|
if (hal->in_flight_head) {
|
|
|
|
send_new_packet(hal);
|
|
|
|
ret = ESP_OK;
|
|
|
|
} else {
|
|
|
|
ret = ESP_ERR_NOT_FOUND;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t send_write_desc(uint8_t* desc, void* arg)
|
|
|
|
{
|
|
|
|
sdio_slave_hal_send_desc_t* next_desc = SEND_DESC_NEXT(desc);
|
|
|
|
memcpy(desc, arg, sizeof(sdio_slave_hal_send_desc_t));
|
|
|
|
SEND_DESC_NEXT_SET(desc, next_desc);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void send_isr_invoke(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_send_part_done_intr_ena(hal->slc, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t sdio_slave_hal_send_queue(sdio_slave_context_t* hal, uint8_t *addr, size_t len, void *arg)
|
|
|
|
{
|
|
|
|
hal->tail_pkt_len += len;
|
|
|
|
sdio_slave_hal_send_desc_t new_desc = {
|
|
|
|
.dma_desc = {
|
|
|
|
.size = len,
|
|
|
|
.length = len,
|
|
|
|
.buf = addr,
|
|
|
|
.owner = 1,
|
|
|
|
// in stream mode, the eof is only appended (in ISR) when new packet is ready to be sent
|
|
|
|
.eof = (hal->sending_mode == SDIO_SLAVE_SEND_PACKET),
|
|
|
|
},
|
|
|
|
.arg = arg,
|
|
|
|
.pkt_len = hal->tail_pkt_len,
|
|
|
|
};
|
|
|
|
|
|
|
|
esp_err_t ret = sdio_ringbuf_send(&(hal->send_desc_queue), send_write_desc, &new_desc);
|
|
|
|
send_isr_invoke(hal);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------------
|
|
|
|
* Receive
|
|
|
|
*--------------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
static lldesc_t* recv_get_first_empty_buf(sdio_slave_context_t* hal)
|
|
|
|
{
|
|
|
|
sdio_slave_hal_recv_stailq_t *const queue = &(hal->recv_link_list);
|
|
|
|
lldesc_t *desc = STAILQ_FIRST(queue);
|
|
|
|
while(desc && desc->owner == 0) {
|
|
|
|
desc = STAILQ_NEXT(desc, qe);
|
|
|
|
}
|
|
|
|
return desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_recv_stop(sdio_slave_context_t* hal)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_set_ioready(hal->hinf, false); //set IO ready to 0 to stop host from using
|
|
|
|
sdio_slave_ll_send_stop(hal->slc);
|
|
|
|
sdio_slave_ll_recv_stop(hal->slc);
|
|
|
|
sdio_slave_ll_recv_intr_ena(hal->slc, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
//touching linked list, should be protected by spinlock
|
|
|
|
bool sdio_slave_hal_recv_has_next_item(sdio_slave_context_t* hal)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (hal->recv_cur_ret == NULL || hal->recv_cur_ret->owner != 0) return false;
|
|
|
|
|
|
|
|
// This may cause the ``cur_ret`` pointer to be NULL, indicating the list is empty,
|
|
|
|
// in this case the ``tx_done`` should happen no longer until new desc is appended.
|
|
|
|
// The app is responsible to place the pointer to the right place again when appending new desc.
|
|
|
|
|
|
|
|
hal->recv_cur_ret = STAILQ_NEXT(hal->recv_cur_ret, qe);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool sdio_slave_hal_recv_done(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
bool ret = sdio_slave_ll_recv_done(hal->slc);
|
|
|
|
if (ret) {
|
|
|
|
sdio_slave_ll_recv_done_clear(hal->slc);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
lldesc_t *sdio_slave_hal_recv_unload_desc(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
sdio_slave_hal_recv_stailq_t *const queue = &hal->recv_link_list;
|
|
|
|
lldesc_t *desc = STAILQ_FIRST(queue);
|
|
|
|
if (desc) {
|
|
|
|
STAILQ_REMOVE_HEAD(queue, qe);
|
|
|
|
}
|
|
|
|
return desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_recv_init_desc(sdio_slave_context_t* hal, lldesc_t *desc, uint8_t *start)
|
|
|
|
{
|
|
|
|
*desc = (lldesc_t) {
|
|
|
|
.size = hal->recv_buffer_size,
|
|
|
|
.buf = start,
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_recv_start(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_recv_reset(hal->slc);
|
|
|
|
lldesc_t *desc = recv_get_first_empty_buf(hal);
|
|
|
|
if (!desc) {
|
|
|
|
HAL_LOGD(TAG, "recv: restart without desc");
|
|
|
|
} else {
|
|
|
|
//the counter is handled when add/flush/reset
|
|
|
|
sdio_slave_ll_recv_start(hal->slc, desc);
|
|
|
|
sdio_slave_ll_recv_intr_ena(hal->slc, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_recv_reset_counter(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_recv_size_reset(hal->slc);
|
|
|
|
lldesc_t *desc = recv_get_first_empty_buf(hal);
|
|
|
|
while (desc != NULL) {
|
|
|
|
sdio_slave_ll_recv_size_inc(hal->slc);
|
|
|
|
desc = STAILQ_NEXT(desc, qe);
|
|
|
|
}
|
|
|
|
}
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|
|
|
|
|
|
|
void sdio_slave_hal_recv_flush_one_buffer(sdio_slave_context_t *hal)
|
|
|
|
{
|
|
|
|
sdio_slave_hal_recv_stailq_t *const queue = &hal->recv_link_list;
|
|
|
|
lldesc_t *desc = STAILQ_FIRST(queue);
|
|
|
|
assert (desc != NULL && desc->owner == 0);
|
|
|
|
STAILQ_REMOVE_HEAD(queue, qe);
|
|
|
|
desc->owner = 1;
|
|
|
|
STAILQ_INSERT_TAIL(queue, desc, qe);
|
|
|
|
sdio_slave_ll_recv_size_inc(hal->slc);
|
|
|
|
//we only add it to the tail here, without start the DMA nor increase buffer num.
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_load_buf(sdio_slave_context_t *hal, lldesc_t *desc)
|
|
|
|
{
|
|
|
|
sdio_slave_hal_recv_stailq_t *const queue = &(hal->recv_link_list);
|
|
|
|
desc->owner = 1;
|
|
|
|
|
|
|
|
lldesc_t *const tail = STAILQ_LAST(queue, lldesc_s, qe);
|
|
|
|
|
|
|
|
STAILQ_INSERT_TAIL(queue, desc, qe);
|
|
|
|
if (hal->recv_cur_ret == NULL) {
|
|
|
|
hal->recv_cur_ret = desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tail == NULL) {
|
|
|
|
//no one in the ll, start new ll operation.
|
|
|
|
sdio_slave_ll_recv_start(hal->slc, desc);
|
|
|
|
sdio_slave_ll_recv_intr_ena(hal->slc, true);
|
|
|
|
HAL_LOGV(TAG, "recv_load_buf: start new");
|
|
|
|
} else {
|
|
|
|
//restart former ll operation
|
|
|
|
sdio_slave_ll_recv_restart(hal->slc);
|
|
|
|
HAL_LOGV(TAG, "recv_load_buf: restart");
|
|
|
|
}
|
|
|
|
sdio_slave_ll_recv_size_inc(hal->slc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void show_queue_item(lldesc_t *item)
|
|
|
|
{
|
2021-09-01 01:58:47 -04:00
|
|
|
HAL_EARLY_LOGI(TAG, "=> %p: size: %d(%d), eof: %d, owner: %d", item, item->size, item->length, item->eof, item->owner);
|
|
|
|
HAL_EARLY_LOGI(TAG, " buf: %p, stqe_next: %p", item->buf, item->qe.stqe_next);
|
2019-10-10 00:35:13 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __attribute((unused)) dump_queue(sdio_slave_hal_recv_stailq_t *queue)
|
|
|
|
{
|
|
|
|
int cnt = 0;
|
|
|
|
lldesc_t *item = NULL;
|
2021-09-01 01:58:47 -04:00
|
|
|
HAL_EARLY_LOGI(TAG, ">>>>> first: %p, last: %p <<<<<", queue->stqh_first, queue->stqh_last);
|
2019-10-10 00:35:13 -04:00
|
|
|
STAILQ_FOREACH(item, queue, qe) {
|
|
|
|
cnt++;
|
|
|
|
show_queue_item(item);
|
|
|
|
}
|
2021-09-01 01:58:47 -04:00
|
|
|
HAL_EARLY_LOGI(TAG, "total: %d", cnt);
|
2019-10-10 00:35:13 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------------
|
|
|
|
* Host
|
|
|
|
*--------------------------------------------------------------------------*/
|
|
|
|
void sdio_slave_hal_hostint_get_ena(sdio_slave_context_t *hal, sdio_slave_hostint_t *out_int_mask)
|
|
|
|
{
|
|
|
|
*out_int_mask = sdio_slave_ll_host_get_intena(hal->host);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_hostint_clear(sdio_slave_context_t *hal, const sdio_slave_hostint_t *mask)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_host_intr_clear(hal->host, mask);//clear all interrupts
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_hostint_set_ena(sdio_slave_context_t *hal, const sdio_slave_hostint_t *mask)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_host_set_intena(hal->host, mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_hostint_send(sdio_slave_context_t *hal, const sdio_slave_hostint_t *mask)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_host_send_int(hal->slc, mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t sdio_slave_hal_host_get_reg(sdio_slave_context_t *hal, int pos)
|
|
|
|
{
|
|
|
|
return sdio_slave_ll_host_get_reg(hal->host, pos);
|
|
|
|
}
|
|
|
|
void sdio_slave_hal_host_set_reg(sdio_slave_context_t *hal, int pos, uint8_t reg)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_host_set_reg(hal->host, pos, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sdio_slave_hal_slvint_fetch_clear(sdio_slave_context_t *hal, sdio_slave_ll_slvint_t *out_int_mask)
|
|
|
|
{
|
|
|
|
sdio_slave_ll_slvint_fetch_clear(hal->slc, out_int_mask);
|
|
|
|
}
|