2016-08-24 05:21:27 -04:00
|
|
|
#ifndef PANIC_H
|
|
|
|
#define PANIC_H
|
|
|
|
|
2017-01-17 18:57:53 -05:00
|
|
|
#ifdef __cplusplus
|
|
|
|
extern "C"
|
|
|
|
{
|
|
|
|
#endif
|
2016-10-25 05:05:13 -04:00
|
|
|
|
|
|
|
#define PANIC_RSN_NONE 0
|
|
|
|
#define PANIC_RSN_DEBUGEXCEPTION 1
|
|
|
|
#define PANIC_RSN_DOUBLEEXCEPTION 2
|
|
|
|
#define PANIC_RSN_KERNELEXCEPTION 3
|
|
|
|
#define PANIC_RSN_COPROCEXCEPTION 4
|
2016-10-25 06:08:55 -04:00
|
|
|
#define PANIC_RSN_INTWDT_CPU0 5
|
|
|
|
#define PANIC_RSN_INTWDT_CPU1 6
|
2017-03-09 07:50:39 -05:00
|
|
|
#define PANIC_RSN_CACHEERR 7
|
|
|
|
#define PANIC_RSN_MAX 7
|
2016-10-25 05:05:13 -04:00
|
|
|
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLER__
|
|
|
|
|
2017-01-09 03:42:45 -05:00
|
|
|
#include "esp_err.h"
|
2020-04-23 21:51:58 -04:00
|
|
|
#include "soc/soc.h"
|
2017-01-09 03:42:45 -05:00
|
|
|
|
2017-01-10 00:05:19 -05:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
|
|
|
|
* address. Do nothing otherwise.
|
|
|
|
* @param data Pointer to the target breakpoint position
|
|
|
|
*/
|
|
|
|
|
2016-10-26 00:23:01 -04:00
|
|
|
void esp_set_breakpoint_if_jtag(void *fn);
|
2016-08-24 05:21:27 -04:00
|
|
|
|
2017-01-09 03:42:45 -05:00
|
|
|
#define ESP_WATCHPOINT_LOAD 0x40000000
|
|
|
|
#define ESP_WATCHPOINT_STORE 0x80000000
|
|
|
|
#define ESP_WATCHPOINT_ACCESS 0xC0000000
|
|
|
|
|
2017-01-10 00:05:19 -05:00
|
|
|
/**
|
|
|
|
* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
|
|
|
|
*
|
|
|
|
* @param no Watchpoint number. On the ESP32, this can be 0 or 1.
|
|
|
|
* @param adr Base address to watch
|
|
|
|
* @param size Size of the region, starting at the base address, to watch. Must
|
|
|
|
* be one of 2^n, with n in [0..6].
|
|
|
|
* @param flags One of ESP_WATCHPOINT_* flags
|
|
|
|
*
|
|
|
|
* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
|
|
|
|
*
|
|
|
|
* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
|
|
|
|
* masking away the lower n bits for a region with size 2^n. If adr does
|
|
|
|
* not have zero for these lower n bits, you may not be watching the
|
|
|
|
* region you intended.
|
|
|
|
*/
|
2017-01-09 03:42:45 -05:00
|
|
|
esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
|
2017-01-10 00:05:19 -05:00
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Clear a watchpoint
|
|
|
|
*
|
|
|
|
* @param no Watchpoint to clear
|
|
|
|
*
|
|
|
|
*/
|
2017-01-09 03:42:45 -05:00
|
|
|
void esp_clear_watchpoint(int no);
|
|
|
|
|
2020-04-23 21:51:58 -04:00
|
|
|
/**
|
|
|
|
* @brief Checks stack pointer in dram
|
|
|
|
*/
|
|
|
|
inline static bool esp_stack_ptr_in_dram(uint32_t sp)
|
|
|
|
{
|
|
|
|
//Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
|
|
|
|
return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
|
|
|
|
}
|
|
|
|
|
|
|
|
#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
|
|
|
|
/**
|
|
|
|
* @brief Checks stack pointer in external ram
|
|
|
|
*/
|
|
|
|
inline static bool esp_stack_ptr_in_extram(uint32_t sp)
|
|
|
|
{
|
|
|
|
//Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned.
|
|
|
|
return !(sp < SOC_EXTRAM_DATA_LOW + 0x10 || sp > SOC_EXTRAM_DATA_HIGH - 0x10 || ((sp & 0xF) != 0));
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-04-20 12:38:38 -04:00
|
|
|
/**
|
|
|
|
* @brief Checks stack pointer
|
|
|
|
*/
|
|
|
|
static inline bool esp_stack_ptr_is_sane(uint32_t sp)
|
|
|
|
{
|
2020-04-23 21:51:58 -04:00
|
|
|
#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
|
|
|
|
return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp));
|
|
|
|
#else
|
|
|
|
return esp_stack_ptr_in_dram(sp);
|
|
|
|
#endif
|
2017-04-20 12:38:38 -04:00
|
|
|
}
|
2016-10-25 05:05:13 -04:00
|
|
|
#endif
|
2016-08-24 05:21:27 -04:00
|
|
|
|
2017-01-17 18:57:53 -05:00
|
|
|
#ifdef __cplusplus
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-01-10 00:05:19 -05:00
|
|
|
#endif
|