2019-11-27 20:20:00 -05:00
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "hal/spi_flash_hal.h"
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#include "string.h"
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#include "hal/hal_defs.h"
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#include "sdkconfig.h"
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#define ADDRESS_MASK_24BIT 0xFFFFFF
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2020-05-07 02:46:41 -04:00
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#define COMPUTE_DUMMY_CYCLELEN(host, base) ((base) + ((spi_flash_hal_context_t*)host)->extra_dummy)
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2019-11-27 20:20:00 -05:00
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2020-05-07 02:46:41 -04:00
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static inline spi_dev_t *get_spi_dev(spi_flash_host_inst_t *host)
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2019-11-27 20:20:00 -05:00
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{
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return ((spi_flash_hal_context_t*)host)->spi;
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2019-11-27 20:20:00 -05:00
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}
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2020-05-07 02:46:41 -04:00
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void spi_flash_hal_poll_cmd_done(spi_flash_host_inst_t *host)
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2019-11-27 20:20:00 -05:00
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{
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while (!spi_flash_ll_cmd_is_done(get_spi_dev(host))) {
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//nop
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}
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}
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2020-05-07 02:46:41 -04:00
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esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host)
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2019-11-27 20:20:00 -05:00
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{
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_reset(dev);
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2020-05-07 02:46:41 -04:00
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spi_flash_ll_set_cs_pin(dev, ((spi_flash_hal_context_t*)host)->cs_num);
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spi_flash_ll_set_clock(dev, &((spi_flash_hal_context_t*)host)->clock_conf);
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2019-11-27 20:20:00 -05:00
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_configure_host_io_mode(
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spi_flash_host_inst_t *host,
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uint32_t command,
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uint32_t addr_bitlen,
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int dummy_cyclelen_base,
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esp_flash_io_mode_t io_mode)
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{
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spi_dev_t *dev = get_spi_dev(host);
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2020-05-11 14:31:30 -04:00
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int host_id = spi_flash_ll_hw_get_id(dev);
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2019-11-27 20:20:00 -05:00
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2020-05-11 14:31:30 -04:00
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if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) {
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2019-11-27 20:20:00 -05:00
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return ESP_ERR_NOT_SUPPORTED;
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}
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2020-05-11 14:31:30 -04:00
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if (addr_bitlen > 24 && SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id)) {
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2020-02-09 20:05:34 -05:00
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/*
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* The extra address bits (24-addr_bitlen) are used to control the M7-M0 bits right after
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* the address field, to avoid the flash going into continuous read mode.
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*
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* On ESP32-S2 the MEMSPI (that SUPPORT_CONTROL_DUMMY_OUTPUT), the least significant
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* addr_bitlen bits of the address will be used, instead of the MSBs. The driver is
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* required to set the address according to the extra address bits.
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*
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* To reduce the time consuming for the read() function to calculate the shift of address,
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* the addr_bitlen is kept to 24 bits. And the CONTROL_DUMMY_OUTPUT feature is used to
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* control those bits instead.
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*/
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//This block is only reached when SPI_FLASH_QIO or SPI_FLASH_DIO
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assert(io_mode == SPI_FLASH_DIO || io_mode == SPI_FLASH_QIO);
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int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
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dummy_cyclelen_base += (addr_bitlen - 24) / line_width;
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addr_bitlen = 24;
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spi_flash_ll_set_dummy_out(dev, 1, 1);
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}
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2019-11-27 20:20:00 -05:00
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spi_flash_ll_set_command8(dev, command);
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spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
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// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
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spi_flash_ll_set_dummy(dev, COMPUTE_DUMMY_CYCLELEN(host, dummy_cyclelen_base));
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//disable all data phases, enable them later if needed
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spi_flash_ll_set_miso_bitlen(dev, 0);
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spi_flash_ll_set_mosi_bitlen(dev, 0);
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spi_flash_ll_set_read_mode(dev, io_mode);
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return ESP_OK;
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}
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2020-05-07 02:46:41 -04:00
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esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans)
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{
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host->driver->configure_host_io_mode(host, trans->command, trans->address_bitlen, 0, SPI_FLASH_FASTRD);
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2019-11-27 20:20:00 -05:00
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spi_dev_t *dev = get_spi_dev(host);
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//disable dummy if no input phase
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if (trans->miso_len == 0) {
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spi_flash_ll_set_dummy(dev, 0);
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}
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2020-01-17 02:14:13 -05:00
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spi_flash_ll_set_usr_address(dev, (trans->address & ADDRESS_MASK_24BIT), spi_flash_ll_get_addr_bitlen(dev));
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2019-11-27 20:20:00 -05:00
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spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len * 8);
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spi_flash_ll_set_buffer_data(dev, trans->mosi_data, trans->mosi_len);
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spi_flash_ll_set_miso_bitlen(dev, trans->miso_len * 8);
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spi_flash_ll_user_start(dev);
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host->driver->poll_cmd_done(host);
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2019-11-27 20:20:00 -05:00
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spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len);
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return ESP_OK;
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}
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2020-05-07 02:46:41 -04:00
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esp_err_t spi_flash_hal_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len)
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2019-11-27 20:20:00 -05:00
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{
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spi_dev_t *dev = get_spi_dev(host);
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2020-02-05 11:28:18 -05:00
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int bitlen = spi_flash_ll_get_addr_bitlen(dev);
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spi_flash_ll_set_usr_address(dev, address << (bitlen - 24), bitlen);
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2019-11-27 20:20:00 -05:00
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spi_flash_ll_set_miso_bitlen(dev, read_len * 8);
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spi_flash_ll_user_start(dev);
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2020-05-07 02:46:41 -04:00
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host->driver->poll_cmd_done(host);
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2019-11-27 20:20:00 -05:00
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spi_flash_ll_get_buffer_data(dev, buffer, read_len);
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return ESP_OK;
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}
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