2022-05-09 05:33:51 -04:00
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/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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2022-05-24 05:26:36 -04:00
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "driver/dac_types_legacy.h"
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#include "hal/adc_ll.h"
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#include "hal/dac_ll.h"
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2022-05-09 05:33:51 -04:00
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#include "esp_check.h"
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#include "esp_pm.h"
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static __attribute__((unused)) const char *TAG = "DAC";
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define DAC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define DAC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_dac_digi_lock = NULL;
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#endif //CONFIG_PM_ENABLE
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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esp_err_t dac_digi_init(void)
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{
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DAC_ENTER_CRITICAL();
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2022-05-24 05:26:36 -04:00
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dac_ll_digi_clk_inv(true);
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_digi_deinit(void)
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{
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#ifdef CONFIG_PM_ENABLE
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if (s_dac_digi_lock) {
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esp_pm_lock_delete(s_dac_digi_lock);
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s_dac_digi_lock = NULL;
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}
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#endif
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DAC_ENTER_CRITICAL();
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dac_ll_digi_trigger_output(false);
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dac_ll_digi_enable_dma(false);
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dac_ll_digi_fifo_reset();
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dac_ll_digi_reset();
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg)
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{
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ESP_RETURN_ON_FALSE(cfg->mode <= DAC_CONV_ALTER, ESP_ERR_INVALID_ARG, TAG, "DAC mode error");
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ESP_RETURN_ON_FALSE(cfg->interval > 0 && cfg->interval < 4096, ESP_ERR_INVALID_ARG, TAG, "DAC interval error");
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ESP_RETURN_ON_FALSE(cfg->dig_clk.div_num < 256, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_num error");
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ESP_RETURN_ON_FALSE(cfg->dig_clk.div_b > 0 && cfg->dig_clk.div_b < 64, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_b error");
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ESP_RETURN_ON_FALSE(cfg->dig_clk.div_a < 64, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_a error");
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#ifdef CONFIG_PM_ENABLE
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esp_err_t err;
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if (s_dac_digi_lock == NULL) {
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if (cfg->dig_clk.use_apll) {
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err = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "dac_dma", &s_dac_digi_lock);
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} else {
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err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "dac_dma", &s_dac_digi_lock);
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}
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if (err != ESP_OK) {
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s_dac_digi_lock = NULL;
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ESP_LOGE(TAG, "DAC-DMA pm lock error");
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return err;
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}
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}
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#endif //CONFIG_PM_ENABLE
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DAC_ENTER_CRITICAL();
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dac_ll_digi_set_convert_mode(cfg->mode == DAC_CONV_ALTER);
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dac_ll_digi_set_trigger_interval(cfg->interval);
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adc_ll_digi_controller_clk_div(cfg->dig_clk.div_num, cfg->dig_clk.div_b, cfg->dig_clk.div_a);
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adc_ll_digi_clk_sel(cfg->dig_clk.use_apll);
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_digi_start(void)
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{
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#ifdef CONFIG_PM_ENABLE
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ESP_RETURN_ON_FALSE(s_dac_digi_lock, ESP_FAIL, TAG, "Should start after call `dac_digi_controller_config`");
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esp_pm_lock_acquire(s_dac_digi_lock);
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#endif
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DAC_ENTER_CRITICAL();
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dac_ll_digi_enable_dma(true);
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dac_ll_digi_trigger_output(true);
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_digi_stop(void)
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{
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#ifdef CONFIG_PM_ENABLE
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if (s_dac_digi_lock) {
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esp_pm_lock_release(s_dac_digi_lock);
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}
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#endif
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DAC_ENTER_CRITICAL();
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2022-05-24 05:26:36 -04:00
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dac_ll_digi_trigger_output(false);
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dac_ll_digi_enable_dma(false);
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_digi_fifo_reset(void)
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{
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DAC_ENTER_CRITICAL();
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2022-05-24 05:26:36 -04:00
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dac_ll_digi_fifo_reset();
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_digi_reset(void)
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{
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DAC_ENTER_CRITICAL();
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dac_ll_digi_reset();
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2022-05-09 05:33:51 -04:00
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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