esp-idf/examples/system/ulp/ulp_riscv/interrupts/sdkconfig.defaults

# Enable ULP
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_TYPE_RISCV=y
CONFIG_ULP_COPROC_RESERVE_MEM=4096
CONFIG_ULP_RISCV_INTERRUPT_ENABLE=y
# Set log level to Warning to produce clean output
CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
CONFIG_BOOTLOADER_LOG_LEVEL=2
CONFIG_LOG_DEFAULT_LEVEL_WARN=y
CONFIG_LOG_DEFAULT_LEVEL=2
feat(ulp-riscv): Added new example to demonstrate ULP RISC-V interrupts This commit adds a new example which demonstrates how the ULP RISC-V co-processor handles interrupts. 2023-12-14 10:15:06 -05:00			`# Enable ULP`
			`CONFIG_ULP_COPROC_ENABLED=y`
			`CONFIG_ULP_COPROC_TYPE_RISCV=y`
			`CONFIG_ULP_COPROC_RESERVE_MEM=4096`
feat(ulp-riscv): Added Kconfig option to enable ULP RISC-V interrupts This commit adds a Kconfig option, CONFIG_ULP_RISCV_INTERRUPT_ENABLE, to enable interrupts on the ULP RISC-V core on the esp32s2 and esp32s3. 2024-02-12 07:40:57 -05:00			`CONFIG_ULP_RISCV_INTERRUPT_ENABLE=y`
feat(ulp-riscv): Added new example to demonstrate ULP RISC-V interrupts This commit adds a new example which demonstrates how the ULP RISC-V co-processor handles interrupts. 2023-12-14 10:15:06 -05:00			`# Set log level to Warning to produce clean output`
			`CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y`
			`CONFIG_BOOTLOADER_LOG_LEVEL=2`
			`CONFIG_LOG_DEFAULT_LEVEL_WARN=y`
			`CONFIG_LOG_DEFAULT_LEVEL=2`