2021-11-02 04:57:03 -04:00
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-04-10 04:24:50 -04:00
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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#include "esp_log.h"
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2021-04-01 08:00:54 -04:00
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#include "esp_check.h"
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2022-05-27 03:06:42 -04:00
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#include "esp_eth_driver.h"
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2019-04-10 04:24:50 -04:00
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#include "eth_phy_regs_struct.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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2019-11-13 23:03:14 -05:00
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#include "driver/gpio.h"
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2020-06-19 00:00:58 -04:00
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#include "esp_rom_gpio.h"
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2020-07-21 01:07:34 -04:00
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#include "esp_rom_sys.h"
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2019-04-10 04:24:50 -04:00
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2021-06-24 04:31:33 -04:00
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static const char *TAG = "lan87xx";
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/***************List of Supported Models***************/
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// See Microchip's Application Note AN25.3 summarizing differences among below models
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#define LAN8710A_MODEL_NUM 0x0F
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#define LAN8720A_MODEL_NUM 0x0F
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#define LAN8740A_MODEL_NUM 0x11
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#define LAN8741A_MODEL_NUM 0x12
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#define LAN8742A_MODEL_NUM 0x13
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static const uint8_t supported_models[] = {
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LAN8710A_MODEL_NUM,
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#if (LAN8710A_MODEL_NUM != LAN8720A_MODEL_NUM)
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LAN8720A_MODEL_NUM,
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#endif
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LAN8740A_MODEL_NUM,
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LAN8741A_MODEL_NUM,
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LAN8742A_MODEL_NUM
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};
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2019-04-10 04:24:50 -04:00
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/***************Vendor Specific Register***************/
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/**
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* @brief MCSR(Mode Control Status Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 1; /* Reserved */
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uint32_t energy_is_on : 1; /* Energy is On */
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uint32_t reserved2 : 4; /* Reserved */
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uint32_t en_alternate_interrupt : 1; /* Enable Alternate Interrupt Mode */
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uint32_t reserved3 : 2; /* Reserved */
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uint32_t en_far_loopback : 1; /* Enable Far Loopback Mode */
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uint32_t reserved4 : 3; /* Reserved */
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uint32_t en_energy_detect_powerdown : 1; /* Enable Energy Detect Power Down */
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uint32_t reserved5 : 2; /* Reserved */
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};
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uint32_t val;
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} mcsr_reg_t;
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#define ETH_PHY_MCSR_REG_ADDR (0x11)
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/**
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* @brief SMR(Special Modes Register)
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*
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*/
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typedef union {
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struct {
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2021-08-05 11:37:27 -04:00
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uint32_t phy_addr : 5; /* PHY Address */
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uint32_t mode : 3; /* Transceiver Mode of Operation */
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uint32_t reserved_1 : 6; /* Reserved */
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uint32_t mii_mode : 1; /* Mode of the digital interface (only LAN8710A/LAN8740A/LAN8741A) */
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uint32_t reserved_2 : 1; /* Reserved */
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2019-04-10 04:24:50 -04:00
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};
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uint32_t val;
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} smr_reg_t;
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#define ETH_PHY_SMR_REG_ADDR (0x12)
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2021-08-05 11:37:27 -04:00
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/**
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* @brief Time Domain Reflectometry Patterns/Delay Control Register
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* Only available in LAN8740A/LAN8742A
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*/
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typedef union {
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struct {
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uint32_t tdr_pattern_low : 6; /* Data pattern sent in TDR mode for the low cycle */
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uint32_t tdr_pattern_high : 6; /* Data pattern sent in TDR mode for the high cycle */
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uint32_t tdr_line_break_counter : 3; /* Increments of 256ms of break time */
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uint32_t tdr_delay_in : 1; /* Line break counter used */
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};
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uint32_t val;
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} tdr_pattern_reg_t;
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#define EHT_PHY_TDRPD_REG_ADDR (0x18)
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/**
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* @brief Time Domain Reflectometry Control/Status Register)
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* Only available in LAN8740A/LAN8742A
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*/
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typedef union {
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struct {
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uint32_t tdr_channel_length : 8; /* TDR channel length */
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uint32_t tdr_channel_status : 1; /* TDR channel status */
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uint32_t tdr_channel_cable_type : 2; /* TDR channel cable type */
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uint32_t reserved : 3; /* Reserved */
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uint32_t tdr_a2d_filter_enable: 1; /* Analog to Digital Filter Enabled */
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uint32_t tdr_enable : 1; /* Enable TDR */
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};
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uint32_t val;
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} tdr_control_reg_t;
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#define EHT_PHY_TDRC_REG_ADDR (0x19)
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2019-04-10 04:24:50 -04:00
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/**
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* @brief SECR(Symbol Error Counter Register)
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*
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*/
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typedef union {
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struct {
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uint32_t symbol_err_count : 16; /* Symbol Error Counter */
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};
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uint32_t val;
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} secr_reg_t;
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#define EHT_PHY_SECR_REG_ADDR (0x1A)
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/**
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* @brief CSIR(Control Status Indications Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 4; /* Reserved */
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uint32_t base10_t_polarity : 1; /* Polarity State of 10Base-T */
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uint32_t reserved2 : 6; /* Reserved */
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uint32_t dis_sqe : 1; /* Disable SQE test(Heartbeat) */
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uint32_t reserved3 : 1; /* Reserved */
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uint32_t select_channel : 1; /* Manual channel select:MDI(0) or MDIX(1) */
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uint32_t reserved4 : 1; /* Reserved */
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uint32_t auto_mdix_ctrl : 1; /* Auto-MDIX Control: EN(0) or DE(1) */
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};
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uint32_t val;
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} scsir_reg_t;
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#define ETH_PHY_CSIR_REG_ADDR (0x1B)
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2021-08-05 11:37:27 -04:00
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/**
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* @brief Cable Length Register
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* Only available in LAN8740A/LAN8742A
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*/
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typedef union {
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struct {
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uint32_t reserved : 12; /* Reserved */
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uint32_t cable_length : 4; /* Cable length */
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};
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uint32_t val;
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} cbln_reg_t;
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#define EHT_PHY_CBLN_REG_ADDR (0x1C)
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2019-04-10 04:24:50 -04:00
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/**
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* @brief ISR(Interrupt Source Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 1; /* Reserved */
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uint32_t auto_nego_page_received : 1; /* Auto-Negotiation Page Received */
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2021-01-27 10:44:13 -05:00
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uint32_t parallel_detect_fault : 1; /* Parallel Detection Fault */
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2019-04-10 04:24:50 -04:00
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uint32_t auto_nego_lp_acknowledge : 1; /* Auto-Negotiation LP Acknowledge */
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uint32_t link_down : 1; /* Link Down */
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uint32_t remote_fault_detect : 1; /* Remote Fault Detect */
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uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
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2021-08-05 11:37:27 -04:00
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uint32_t energy_on_generate : 1; /* ENERGY ON generated */
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uint32_t wake_on_lan : 1; /* Wake on Lan (WOL) event detected (only LAN8740A/LAN8742A) */
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uint32_t reserved2 : 7; /* Reserved */
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2019-04-10 04:24:50 -04:00
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};
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uint32_t val;
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} isfr_reg_t;
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#define ETH_PHY_ISR_REG_ADDR (0x1D)
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/**
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* @brief IMR(Interrupt Mask Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 1; /* Reserved */
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uint32_t auto_nego_page_received : 1; /* Auto-Negotiation Page Received */
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2021-01-27 10:44:13 -05:00
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uint32_t parallel_detect_fault : 1; /* Parallel Detection Fault */
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2019-04-10 04:24:50 -04:00
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uint32_t auto_nego_lp_acknowledge : 1; /* Auto-Negotiation LP Acknowledge */
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uint32_t link_down : 1; /* Link Down */
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uint32_t remote_fault_detect : 1; /* Remote Fault Detect */
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uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
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2021-01-27 10:44:13 -05:00
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uint32_t energy_on_generate : 1; /* ENERGY ON generated */
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2021-08-05 11:37:27 -04:00
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uint32_t wake_on_lan : 1; /* Wake on Lan (WOL) event detected (only LAN8740A/LAN8742A) */
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uint32_t reserved2 : 7; /* Reserved */
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2019-04-10 04:24:50 -04:00
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};
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uint32_t val;
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} imr_reg_t;
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#define ETH_PHY_IMR_REG_ADDR (0x1E)
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/**
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* @brief PSCSR(PHY Special Control Status Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 2; /* Reserved */
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uint32_t speed_indication : 3; /* Speed Indication */
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2021-08-05 11:37:27 -04:00
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uint32_t reserved2 : 1; /* Reserved */
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uint32_t enable_4b5b : 1; /* Enable 4B5B encoder (only LAN8740A/LAN8741A) */
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uint32_t reserved3 : 5; /* Reserved */
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2019-04-10 04:24:50 -04:00
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uint32_t auto_nego_done : 1; /* Auto Negotiation Done */
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2021-08-05 11:37:27 -04:00
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uint32_t reserved4 : 3; /* Reserved */
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2019-04-10 04:24:50 -04:00
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};
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uint32_t val;
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} pscsr_reg_t;
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#define ETH_PHY_PSCSR_REG_ADDR (0x1F)
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typedef struct {
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esp_eth_phy_t parent;
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esp_eth_mediator_t *eth;
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2020-11-16 23:48:35 -05:00
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int addr;
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2019-04-10 04:24:50 -04:00
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uint32_t reset_timeout_ms;
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uint32_t autonego_timeout_ms;
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eth_link_t link_status;
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2019-11-13 23:03:14 -05:00
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int reset_gpio_num;
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2021-06-24 04:31:33 -04:00
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} phy_lan87xx_t;
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2019-04-10 04:24:50 -04:00
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2021-06-24 04:31:33 -04:00
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static esp_err_t lan87xx_update_link_duplex_speed(phy_lan87xx_t *lan87xx)
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2019-09-18 23:27:42 -04:00
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{
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2021-04-01 08:00:54 -04:00
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esp_err_t ret = ESP_OK;
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2021-06-24 04:31:33 -04:00
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esp_eth_mediator_t *eth = lan87xx->eth;
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2019-09-18 23:27:42 -04:00
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eth_speed_t speed = ETH_SPEED_10M;
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eth_duplex_t duplex = ETH_DUPLEX_HALF;
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bmsr_reg_t bmsr;
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pscsr_reg_t pscsr;
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2020-07-20 08:42:52 -04:00
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uint32_t peer_pause_ability = false;
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anlpar_reg_t anlpar;
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2021-06-24 04:31:33 -04:00
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
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2019-09-18 23:27:42 -04:00
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eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
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/* check if link status changed */
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2021-06-24 04:31:33 -04:00
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if (lan87xx->link_status != link) {
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2019-09-18 23:27:42 -04:00
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/* when link up, read negotiation result */
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if (link == ETH_LINK_UP) {
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2021-06-24 04:31:33 -04:00
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_PSCSR_REG_ADDR, &(pscsr.val)), err, TAG, "read PSCSR failed");
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2019-09-18 23:27:42 -04:00
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switch (pscsr.speed_indication) {
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case 1: //10Base-T half-duplex
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speed = ETH_SPEED_10M;
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duplex = ETH_DUPLEX_HALF;
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break;
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case 2: //100Base-TX half-duplex
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speed = ETH_SPEED_100M;
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duplex = ETH_DUPLEX_HALF;
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break;
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case 5: //10Base-T full-duplex
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speed = ETH_SPEED_10M;
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duplex = ETH_DUPLEX_FULL;
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break;
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case 6: //100Base-TX full-duplex
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speed = ETH_SPEED_100M;
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duplex = ETH_DUPLEX_FULL;
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break;
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default:
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break;
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}
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
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2020-07-20 08:42:52 -04:00
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/* if we're in duplex mode, and peer has the flow control ability */
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if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
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peer_pause_ability = 1;
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} else {
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peer_pause_ability = 0;
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}
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
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2019-09-18 23:27:42 -04:00
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}
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
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2021-06-24 04:31:33 -04:00
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lan87xx->link_status = link;
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2019-09-18 23:27:42 -04:00
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}
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return ESP_OK;
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err:
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2021-04-01 08:00:54 -04:00
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return ret;
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2019-09-18 23:27:42 -04:00
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}
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2021-06-24 04:31:33 -04:00
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static esp_err_t lan87xx_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
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2019-04-10 04:24:50 -04:00
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{
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2021-04-01 08:00:54 -04:00
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esp_err_t ret = ESP_OK;
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ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mediator to null");
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2021-06-24 04:31:33 -04:00
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phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
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lan87xx->eth = eth;
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2019-04-10 04:24:50 -04:00
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return ESP_OK;
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err:
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2021-04-01 08:00:54 -04:00
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return ret;
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2019-04-10 04:24:50 -04:00
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}
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2021-06-24 04:31:33 -04:00
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static esp_err_t lan87xx_get_link(esp_eth_phy_t *phy)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
2019-09-18 23:27:42 -04:00
|
|
|
/* Updata information about link, speed, duplex */
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(lan87xx_update_link_duplex_speed(lan87xx), err, TAG, "update link duplex speed failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_reset(esp_eth_phy_t *phy)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
lan87xx->link_status = ETH_LINK_DOWN;
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
2019-04-10 04:24:50 -04:00
|
|
|
bmcr_reg_t bmcr = {.reset = 1};
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* wait for reset complete */
|
|
|
|
uint32_t to = 0;
|
2021-06-24 04:31:33 -04:00
|
|
|
for (to = 0; to < lan87xx->reset_timeout_ms / 10; to++) {
|
2019-04-10 04:24:50 -04:00
|
|
|
vTaskDelay(pdMS_TO_TICKS(10));
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
if (!bmcr.reset) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_FALSE(to < lan87xx->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "reset timeout");
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_reset_hw(esp_eth_phy_t *phy)
|
2019-11-13 23:03:14 -05:00
|
|
|
{
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
if (lan87xx->reset_gpio_num >= 0) {
|
|
|
|
esp_rom_gpio_pad_select_gpio(lan87xx->reset_gpio_num);
|
|
|
|
gpio_set_direction(lan87xx->reset_gpio_num, GPIO_MODE_OUTPUT);
|
|
|
|
gpio_set_level(lan87xx->reset_gpio_num, 0);
|
2021-11-01 17:03:30 -04:00
|
|
|
/* assert nRST signal on LAN87xx a little longer than the minimum specified in datasheet */
|
|
|
|
esp_rom_delay_us(150);
|
2021-06-24 04:31:33 -04:00
|
|
|
gpio_set_level(lan87xx->reset_gpio_num, 1);
|
2019-11-13 23:03:14 -05:00
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2021-06-17 01:40:26 -04:00
|
|
|
/**
|
|
|
|
* @note This function is responsible for restarting a new auto-negotiation,
|
|
|
|
* the result of negotiation won't be relected to uppler layers.
|
|
|
|
* Instead, the negotiation result is fetched by linker timer, see `lan87xx_get_link()`
|
|
|
|
*/
|
2021-11-04 04:10:19 -04:00
|
|
|
static esp_err_t lan87xx_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
2021-11-04 04:10:19 -04:00
|
|
|
|
|
|
|
bmcr_reg_t bmcr;
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case ESP_ETH_PHY_AUTONEGO_RESTART:
|
|
|
|
ESP_GOTO_ON_FALSE(bmcr.en_auto_nego, ESP_ERR_INVALID_STATE, err, TAG, "auto negotiation is disabled");
|
|
|
|
/* in case any link status has changed, let's assume we're in link down status */
|
|
|
|
lan87xx->link_status = ETH_LINK_DOWN;
|
|
|
|
|
|
|
|
bmcr.restart_auto_nego = 1; /* Restart Auto Negotiation */
|
|
|
|
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
|
|
|
/* Wait for auto negotiation complete */
|
|
|
|
bmsr_reg_t bmsr;
|
|
|
|
uint32_t to = 0;
|
|
|
|
for (to = 0; to < lan87xx->autonego_timeout_ms / 100; to++) {
|
|
|
|
vTaskDelay(pdMS_TO_TICKS(100));
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
|
|
|
|
if (bmsr.auto_nego_complete) {
|
|
|
|
break;
|
|
|
|
}
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
2021-11-04 04:10:19 -04:00
|
|
|
if ((to >= lan87xx->autonego_timeout_ms / 100) && (lan87xx->link_status == ETH_LINK_UP)) {
|
|
|
|
ESP_LOGW(TAG, "auto negotiation timeout");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ESP_ETH_PHY_AUTONEGO_DIS:
|
|
|
|
if (bmcr.en_auto_nego == 1) {
|
|
|
|
bmcr.en_auto_nego = 0; /* Disable Auto Negotiation */
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
|
|
|
/* read configuration back */
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
|
|
|
ESP_GOTO_ON_FALSE(bmcr.en_auto_nego == 0, ESP_FAIL, err, TAG, "disable auto-negotiation failed");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ESP_ETH_PHY_AUTONEGO_EN:
|
|
|
|
if (bmcr.en_auto_nego == 0) {
|
|
|
|
bmcr.en_auto_nego = 1; /* Enable Auto Negotiation */
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
|
|
|
/* read configuration back */
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
|
|
|
ESP_GOTO_ON_FALSE(bmcr.en_auto_nego == 1, ESP_FAIL, err, TAG, "enable auto-negotiation failed");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ESP_ETH_PHY_AUTONEGO_G_STAT:
|
|
|
|
/* do nothing autonego_en_stat is set at the function end */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
2021-11-04 04:10:19 -04:00
|
|
|
|
|
|
|
*autonego_en_stat = bmcr.en_auto_nego;
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_pwrctl(esp_eth_phy_t *phy, bool enable)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
2019-04-10 04:24:50 -04:00
|
|
|
bmcr_reg_t bmcr;
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
if (!enable) {
|
|
|
|
/* General Power Down Mode */
|
|
|
|
bmcr.power_down = 1;
|
|
|
|
} else {
|
|
|
|
/* Normal operation Mode */
|
|
|
|
bmcr.power_down = 0;
|
|
|
|
}
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
if (!enable) {
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
2021-04-01 08:00:54 -04:00
|
|
|
ESP_GOTO_ON_FALSE(bmcr.power_down == 1, ESP_FAIL, err, TAG, "power down failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
} else {
|
2020-07-30 03:23:36 -04:00
|
|
|
/* wait for power up complete */
|
|
|
|
uint32_t to = 0;
|
2021-06-24 04:31:33 -04:00
|
|
|
for (to = 0; to < lan87xx->reset_timeout_ms / 10; to++) {
|
2020-07-30 03:23:36 -04:00
|
|
|
vTaskDelay(pdMS_TO_TICKS(10));
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
2020-07-30 03:23:36 -04:00
|
|
|
if (bmcr.power_down == 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_FALSE(to < lan87xx->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "power up timeout");
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_set_addr(esp_eth_phy_t *phy, uint32_t addr)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
lan87xx->addr = addr;
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "addr can't be null");
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
*addr = lan87xx->addr;
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_del(esp_eth_phy_t *phy)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
free(lan87xx);
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_advertise_pause_ability(esp_eth_phy_t *phy, uint32_t ability)
|
2020-07-20 08:42:52 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
2020-07-20 08:42:52 -04:00
|
|
|
/* Set PAUSE function ability */
|
|
|
|
anar_reg_t anar;
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
|
2020-07-20 08:42:52 -04:00
|
|
|
if (ability) {
|
|
|
|
anar.asymmetric_pause = 1;
|
|
|
|
anar.symmetric_pause = 1;
|
|
|
|
} else {
|
|
|
|
anar.asymmetric_pause = 0;
|
|
|
|
anar.symmetric_pause = 0;
|
|
|
|
}
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_ANAR_REG_ADDR, anar.val), err, TAG, "write ANAR failed");
|
2020-07-20 08:42:52 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2020-07-20 08:42:52 -04:00
|
|
|
}
|
|
|
|
|
2021-09-03 11:24:01 -04:00
|
|
|
static esp_err_t lan87xx_loopback(esp_eth_phy_t *phy, bool enable)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
|
|
|
/* Set Loopback function */
|
|
|
|
bmcr_reg_t bmcr;
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
|
|
|
if (enable) {
|
|
|
|
bmcr.en_loopback = 1;
|
|
|
|
} else {
|
|
|
|
bmcr.en_loopback = 0;
|
|
|
|
}
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
|
|
|
return ESP_OK;
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-04 04:10:19 -04:00
|
|
|
static esp_err_t lan87xx_set_speed(esp_eth_phy_t *phy, eth_speed_t speed)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
|
|
|
if (lan87xx->link_status == ETH_LINK_UP) {
|
|
|
|
/* Since the link is going to be reconfigured, consider it down for a while */
|
|
|
|
lan87xx->link_status = ETH_LINK_DOWN;
|
|
|
|
/* Indicate to upper stream apps the link is cosidered down */
|
|
|
|
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)lan87xx->link_status), err, TAG, "change link failed");
|
|
|
|
}
|
|
|
|
/* Set speed */
|
|
|
|
bmcr_reg_t bmcr;
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
|
|
|
bmcr.speed_select = speed;
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t lan87xx_set_duplex(esp_eth_phy_t *phy, eth_duplex_t duplex)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
|
|
|
|
|
|
|
if (lan87xx->link_status == ETH_LINK_UP) {
|
|
|
|
/* Since the link is going to be reconfigured, consider it down for a while */
|
|
|
|
lan87xx->link_status = ETH_LINK_DOWN;
|
|
|
|
/* Indicate to upper stream apps the link is cosidered down */
|
|
|
|
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)lan87xx->link_status), err, TAG, "change link failed");
|
|
|
|
}
|
|
|
|
/* Set duplex mode */
|
|
|
|
bmcr_reg_t bmcr;
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
|
|
|
|
bmcr.duplex_mode = duplex;
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_init(esp_eth_phy_t *phy)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = lan87xx->eth;
|
2019-12-23 04:06:02 -05:00
|
|
|
// Detect PHY address
|
2021-06-24 04:31:33 -04:00
|
|
|
if (lan87xx->addr == ESP_ETH_PHY_ADDR_AUTO) {
|
|
|
|
ESP_GOTO_ON_ERROR(esp_eth_detect_phy_addr(eth, &lan87xx->addr), err, TAG, "Detect PHY address failed");
|
2019-12-23 04:06:02 -05:00
|
|
|
}
|
2019-04-10 04:24:50 -04:00
|
|
|
/* Power on Ethernet PHY */
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(lan87xx_pwrctl(phy, true), err, TAG, "power control failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* Reset Ethernet PHY */
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(lan87xx_reset(phy), err, TAG, "reset failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* Check PHY ID */
|
|
|
|
phyidr1_reg_t id1;
|
|
|
|
phyidr2_reg_t id2;
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)), err, TAG, "read ID1 failed");
|
|
|
|
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
|
|
|
|
ESP_GOTO_ON_FALSE(id1.oui_msb == 0x7 && id2.oui_lsb == 0x30, ESP_FAIL, err, TAG, "wrong chip ID");
|
|
|
|
bool supported_model = false;
|
|
|
|
for (unsigned int i = 0; i < sizeof(supported_models); i++) {
|
|
|
|
if (id2.vendor_model == supported_models[i]) {
|
|
|
|
supported_model = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ESP_GOTO_ON_FALSE(supported_model, ESP_FAIL, err, TAG, "unsupported chip model");
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
static esp_err_t lan87xx_deinit(esp_eth_phy_t *phy)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2019-04-10 04:24:50 -04:00
|
|
|
/* Power off Ethernet PHY */
|
2021-06-24 04:31:33 -04:00
|
|
|
ESP_GOTO_ON_ERROR(lan87xx_pwrctl(phy, false), err, TAG, "power control failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-04-01 08:00:54 -04:00
|
|
|
esp_eth_phy_t *ret = NULL;
|
|
|
|
ESP_GOTO_ON_FALSE(config, NULL, err, TAG, "can't set phy config to null");
|
2021-06-24 04:31:33 -04:00
|
|
|
phy_lan87xx_t *lan87xx = calloc(1, sizeof(phy_lan87xx_t));
|
|
|
|
ESP_GOTO_ON_FALSE(lan87xx, NULL, err, TAG, "calloc lan87xx failed");
|
|
|
|
lan87xx->addr = config->phy_addr;
|
|
|
|
lan87xx->reset_gpio_num = config->reset_gpio_num;
|
|
|
|
lan87xx->reset_timeout_ms = config->reset_timeout_ms;
|
|
|
|
lan87xx->link_status = ETH_LINK_DOWN;
|
|
|
|
lan87xx->autonego_timeout_ms = config->autonego_timeout_ms;
|
|
|
|
lan87xx->parent.reset = lan87xx_reset;
|
|
|
|
lan87xx->parent.reset_hw = lan87xx_reset_hw;
|
|
|
|
lan87xx->parent.init = lan87xx_init;
|
|
|
|
lan87xx->parent.deinit = lan87xx_deinit;
|
|
|
|
lan87xx->parent.set_mediator = lan87xx_set_mediator;
|
2021-11-04 04:10:19 -04:00
|
|
|
lan87xx->parent.autonego_ctrl = lan87xx_autonego_ctrl;
|
2021-06-24 04:31:33 -04:00
|
|
|
lan87xx->parent.get_link = lan87xx_get_link;
|
|
|
|
lan87xx->parent.pwrctl = lan87xx_pwrctl;
|
|
|
|
lan87xx->parent.get_addr = lan87xx_get_addr;
|
|
|
|
lan87xx->parent.set_addr = lan87xx_set_addr;
|
2021-09-03 11:24:01 -04:00
|
|
|
lan87xx->parent.loopback = lan87xx_loopback;
|
2021-11-04 04:10:19 -04:00
|
|
|
lan87xx->parent.set_speed = lan87xx_set_speed;
|
|
|
|
lan87xx->parent.set_duplex = lan87xx_set_duplex;
|
2021-06-24 04:31:33 -04:00
|
|
|
lan87xx->parent.advertise_pause_ability = lan87xx_advertise_pause_ability;
|
|
|
|
lan87xx->parent.del = lan87xx_del;
|
2019-04-10 04:24:50 -04:00
|
|
|
|
2021-06-24 04:31:33 -04:00
|
|
|
return &(lan87xx->parent);
|
2019-04-10 04:24:50 -04:00
|
|
|
err:
|
2021-04-01 08:00:54 -04:00
|
|
|
return ret;
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|