2022-06-07 02:46:23 -04:00
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/assist_debug_reg.h"
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2022-08-08 09:18:46 -04:00
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#include "soc/interrupt_reg.h"
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2022-06-07 02:46:23 -04:00
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#include "esp_attr.h"
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#include "riscv/csr.h"
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#include "riscv/interrupt.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*performance counter*/
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#define CSR_PCER_MACHINE 0x7e0
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#define CSR_PCMR_MACHINE 0x7e1
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#define CSR_PCCR_MACHINE 0x7e2
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/* --------------------------------------------------- CPU Control -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_wait_for_intr(void)
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{
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asm volatile ("wfi\n");
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}
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/* -------------------------------------------------- CPU Registers ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR __attribute__((pure)) uint32_t rv_utils_get_core_id(void)
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{
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#if SOC_CPU_CORES_NUM == 1
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return 0; // No need to check core ID on single core hardware
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#else
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uint32_t cpuid;
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cpuid = RV_READ_CSR(mhartid);
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return cpuid;
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#endif
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}
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FORCE_INLINE_ATTR void *rv_utils_get_sp(void)
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{
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void *sp;
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asm volatile ("mv %0, sp;" : "=r" (sp));
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return sp;
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}
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_get_cycle_count(void)
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{
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return RV_READ_CSR(CSR_PCCR_MACHINE);
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}
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_set_cycle_count(uint32_t ccount)
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{
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RV_WRITE_CSR(CSR_PCCR_MACHINE, ccount);
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}
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/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// ---------------- Interrupt Descriptors ------------------
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// --------------- Interrupt Configuration -----------------
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FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
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{
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mtvec_val |= 1; // Set MODE field to treat MTVEC as a vector base address
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RV_WRITE_CSR(mtvec, mtvec_val);
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}
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// ------------------ Interrupt Control --------------------
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FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask)
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{
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2022-07-26 10:07:58 -04:00
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// Disable all interrupts to make updating of the interrupt mask atomic.
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2022-06-07 02:46:23 -04:00
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_intc_int_enable(intr_mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask)
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{
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2022-07-26 10:07:58 -04:00
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// Disable all interrupts to make updating of the interrupt mask atomic.
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2022-06-07 02:46:23 -04:00
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_intc_int_disable(intr_mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
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{
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return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
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}
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2023-04-25 02:32:36 -04:00
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FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(unsigned int intr_num)
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2022-06-07 02:46:23 -04:00
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{
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REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
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}
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2022-07-26 10:07:58 -04:00
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FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void)
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{
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RV_SET_CSR(mstatus, MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void)
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{
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RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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}
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2022-06-07 02:46:23 -04:00
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/* -------------------------------------------------- Memory Ports -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/* ---------------------------------------------------- Debugging ------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------- Breakpoints/Watchpoints -----------------
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FORCE_INLINE_ATTR void rv_utils_set_breakpoint(int bp_num, uint32_t bp_addr)
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{
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/* The code bellow sets breakpoint which will trigger `Breakpoint` exception
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* instead transfering control to debugger. */
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RV_WRITE_CSR(tselect, bp_num);
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2023-04-19 13:37:44 -04:00
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RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE);
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RV_WRITE_CSR(tdata1, TDATA1_USER | TDATA1_MACHINE | TDATA1_EXECUTE);
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2022-06-07 02:46:23 -04:00
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RV_WRITE_CSR(tdata2, bp_addr);
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}
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2023-04-19 08:18:11 -04:00
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FORCE_INLINE_ATTR void rv_utils_set_watchpoint(int wp_num,
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uint32_t wp_addr,
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size_t size,
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bool on_read,
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bool on_write)
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{
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RV_WRITE_CSR(tselect, wp_num);
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2023-04-19 13:37:44 -04:00
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RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE);
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RV_WRITE_CSR(tdata1, TDATA1_USER |
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TDATA1_MACHINE |
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TDATA1_MATCH |
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(on_read ? TDATA1_LOAD : 0) |
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(on_write ? TDATA1_STORE : 0));
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/* From RISC-V Debug Specification:
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* NAPOT (Naturally Aligned Power-Of-Two):
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* Matches when the top M bits of any compare value match the top M bits of tdata2.
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* M is XLEN − 1 minus the index of the least-significant bit containing 0 in tdata2.
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*
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* Note: Expectng that size is number power of 2
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*
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* Examples for understanding how to calculate NAPOT:
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*
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* nnnn...nnnn0 2-byte NAPOT range
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* nnnn...nnn01 4-byte NAPOT range
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* nnnn...nn011 8-byte NAPOT range
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* nnnn...n0111 16-byte NAPOT range
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* nnnn...01111 32-byte NAPOT range
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* * where n are bits from original address
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*/
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const uint32_t half_size = size >> 1;
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uint32_t napot = wp_addr;
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napot &= ~half_size; /* set the least-significant bit with zero */
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napot |= half_size - 1; /* fill all bits with ones after least-significant bit */
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RV_WRITE_CSR(tdata2, napot);
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}
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2022-06-07 02:46:23 -04:00
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FORCE_INLINE_ATTR void rv_utils_clear_breakpoint(int bp_num)
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{
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RV_WRITE_CSR(tselect, bp_num);
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2023-04-19 08:18:11 -04:00
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/* tdata1 is a WARL(write any read legal) register
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* We can just write 0 to it
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*/
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RV_WRITE_CSR(tdata1, 0);
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2022-06-07 02:46:23 -04:00
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}
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2023-04-19 08:18:11 -04:00
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FORCE_INLINE_ATTR void rv_utils_clear_watchpoint(int wp_num)
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{
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2023-04-19 08:18:11 -04:00
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/* riscv have the same registers for breakpoints and watchpoints */
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rv_utils_clear_breakpoint(wp_num);
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2022-06-07 02:46:23 -04:00
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}
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2023-04-19 08:18:11 -04:00
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FORCE_INLINE_ATTR bool rv_utils_is_trigger_fired(int id)
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{
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2023-04-19 08:18:11 -04:00
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RV_WRITE_CSR(tselect, id);
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return (RV_READ_CSR(tdata1) >> TDATA1_HIT_S) & 1;
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2022-06-07 02:46:23 -04:00
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}
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// ---------------------- Debugger -------------------------
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FORCE_INLINE_ATTR bool rv_utils_dbgr_is_attached(void)
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{
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return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
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}
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FORCE_INLINE_ATTR void rv_utils_dbgr_break(void)
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{
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asm volatile("ebreak\n");
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}
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/* ------------------------------------------------------ Misc ---------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value)
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{
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2022-09-19 02:32:54 -04:00
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// ESP32C6 starts to support atomic CAS instructions, but it is still a single core target, no need to implement
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// through lr and sc instructions for now
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// For an RV target has no atomic CAS instruction, we can achieve atomicity by disabling interrupts
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2022-06-07 02:46:23 -04:00
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unsigned old_mstatus;
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old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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// Compare and set
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uint32_t old_value;
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old_value = *addr;
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if (old_value == compare_value) {
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*addr = new_value;
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}
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// Restore interrupts
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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return (old_value == compare_value);
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}
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#ifdef __cplusplus
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}
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#endif
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