uint32_tflash_pe:1;/*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tusr:1;/*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_hpm:1;/*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_res:1;/*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_dp:1;/*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_ce:1;/*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_be:1;/*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_se:1;/*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_pp:1;/*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_tflash_wrsr:1;/*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_rdsr:1;/*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_rdid:1;/*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_wrdi:1;/*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_wren:1;/*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_read:1;/*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_tval;
}cmd;
uint32_taddr;/*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/
uint32_tfdummy_out:1;/*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_tfdout_oct:1;/*Apply 8 signals during write-data phase 1:enable 0: disable*/
uint32_tfdin_oct:1;/*Apply 8 signals during read-data phase 1:enable 0: disable*/
uint32_tfaddr_oct:1;/*Apply 8 signals during address phase 1:enable 0: disable*/
uint32_tfcmd_dual:1;/*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_tfcmd_quad:1;/*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_tfcmd_oct:1;/*Apply 8 signals during command phase 1:enable 0: disable*/
uint32_tfcs_crc_en:1;/*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_ttx_crc_en:1;/*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_treserved12:1;/*reserved*/
uint32_tfastrd_mode:1;/*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
uint32_tclk_mode:2;/*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_tcs_hold_dly_res:12;/*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/
uint32_tcs_hold_dly:12;/*SPI fsm is delayed to idle by spi clock cycles.*/
uint32_tcs_dly_num:2;/*spi_mem_cs signal is delayed by system clock cycles*/
uint32_tcs_dly_mode:2;/*The cs signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/
uint32_treserved30:1;
uint32_tcs_dly_edge:1;/*The bit is used to select the spi clock edge to modify CS line timing.*/
uint32_tsram_wdummy_cyclelen:8;/*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
uint32_treserved30:2;/*reserved*/
};
uint32_tval;
}cache_sctrl;
union{
struct{
uint32_tsclk_mode:2;/*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_tswb_mode:8;/*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_tsdin_dual:1;/*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_tsdout_dual:1;/*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_tsaddr_dual:1;/*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_tscmd_dual:1;/*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_tsdin_quad:1;/*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_tsdout_quad:1;/*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_tsaddr_quad:1;/*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_tscmd_quad:1;/*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_tusr_rd_cmd_value:16;/*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/
uint32_treserved16:12;/*reserved*/
uint32_tusr_rd_cmd_bitlen:4;/*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
};
uint32_tval;
}sram_drd_cmd;
union{
struct{
uint32_tusr_wr_cmd_value:16;/*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
uint32_treserved16:12;/*reserved*/
uint32_tusr_wr_cmd_bitlen:4;/*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/
uint32_tcnt_n:8;/*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_treserved24:7;/*reserved*/
uint32_tequ_sysclk:1;/*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
};
uint32_tval;
}sram_clk;
union{
struct{
uint32_tst:3;/*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_tflash_per:1;/*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_pes:1;/*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tdin0_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin1_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin2_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin3_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tdin4_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_tdin5_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_tdin6_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_tdin7_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_tdins_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_tdout0_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout1_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout2_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout3_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tdout4_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_tdout5_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_tdout6_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_tdout7_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_tdouts_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_tspi_smem_din0_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din1_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din2_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din3_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din4_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din5_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din6_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din7_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_dins_mode:2;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_din0_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din1_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din2_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din3_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din4_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din5_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din6_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_din7_num:3;/*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_dins_num:3;/*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_tspi_smem_dout0_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout1_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout2_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout3_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout4_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout5_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout6_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout7_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_douts_mode:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout0_num:2;/*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_dout1_num:2;/*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_dout2_num:2;/*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_dout3_num:2;/*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_tspi_smem_dout4_num:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout5_num:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout6_num:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_dout7_num:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_smem_douts_num:2;/*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_tspi_fmem_ddr_en:1;/*1: in ddr mode 0 in sdr mode*/
uint32_tspi_fmem_var_dummy:1;/*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_tspi_fmem_ddr_rdat_swp:1;/*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_tspi_fmem_ddr_wdat_swp:1;/*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_tspi_fmem_ddr_cmd_dis:1;/*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_tspi_fmem_outminbytelen:8;/*It is the minimum output data length in the panda device.*/
uint32_tspi_fmem_usr_ddr_dqs_thd:8;/*The delay number of data strobe which from memory based on SPI clock.*/
uint32_tspi_fmem_ddr_dqs_loop:1;/*the data strobe is generated by SPI.*/
uint32_tspi_fmem_ddr_dqs_loop_mode:2;/*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_tspi_smem_ddr_en:1;/*1: in ddr mode 0 in sdr mode*/
uint32_tspi_smem_var_dummy:1;/*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_tspi_smem_ddr_rdat_swp:1;/*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_tspi_smem_ddr_wdat_swp:1;/*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_tspi_smem_ddr_cmd_dis:1;/*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_tspi_smem_outminbytelen:8;/*It is the minimum output data length in the ddr psram.*/
uint32_tspi_smem_usr_ddr_dqs_thd:8;/*The delay number of data strobe which from memory based on SPI clock.*/
uint32_tspi_smem_ddr_dqs_loop:1;/*the data strobe is generated by SPI.*/
uint32_tspi_smem_ddr_dqs_loop_mode:2;/*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_tspi01_clk_sel:2;/*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
