2022-03-02 02:49:31 -05:00
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2017-04-18 05:14:32 -04:00
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "freertos/xtensa_context.h"
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2020-05-29 02:53:30 -04:00
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#include "freertos/xtensa_rtos.h"
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2019-03-26 04:30:43 -04:00
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#include "esp_private/panic_reason.h"
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2017-04-18 05:14:32 -04:00
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#include "sdkconfig.h"
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#include "soc/soc.h"
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2017-05-26 05:41:18 -04:00
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#include "soc/dport_reg.h"
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2020-05-29 02:53:30 -04:00
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#include "soc/timer_group_reg.h"
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2017-04-18 05:14:32 -04:00
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2017-05-26 05:41:18 -04:00
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/*
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2017-04-18 05:14:32 -04:00
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2017-05-26 05:41:18 -04:00
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Interrupt , a high-priority interrupt, is used for several things:
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2021-08-03 02:35:29 -04:00
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- IPC_ISR handler
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2017-05-26 05:41:18 -04:00
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- Cache error panic handler
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- Interrupt watchdog panic handler
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2017-04-18 05:14:32 -04:00
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*/
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2021-09-02 09:10:29 -04:00
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#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
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#define LX_INTR_STACK_SIZE 12
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#define LX_INTR_A2_OFFSET 0
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#define LX_INTR_A3_OFFSET 4
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#define LX_INTR_A4_OFFSET 8
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#define EPC_X EPC_5
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#define EXCSAVE_X EXCSAVE_5
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#define RFI_X 5
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#define xt_highintx xt_highint5
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#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
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#define LX_INTR_STACK_SIZE 12
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#define LX_INTR_A2_OFFSET 0
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#define LX_INTR_A3_OFFSET 4
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#define LX_INTR_A4_OFFSET 8
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#define EPC_X EPC_4
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#define EXCSAVE_X EXCSAVE_4
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#define RFI_X 4
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#define xt_highintx xt_highint4
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#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
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2021-09-01 09:55:50 -04:00
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/*
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--------------------------------------------------------------------------------
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Macro wdt_clr_intr_status - Clear the WDT interrupt status.
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Macro wdt_feed - Feed the WDT.
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Input : "dev" - Beginning address of the peripheral registers
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Macro get_int_status_tg1wdt - Get the ETS_TG1_WDT_LEVEL_INTR_SOURCE bit in interrupt status
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output : "reg" - Store the result into the reg
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--------------------------------------------------------------------------------
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*/
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#define TIMG1_REG_OFFSET(reg) ((reg) - REG_TIMG_BASE(1))
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#define TIMG1_WDTWPROTECT_OFFSET TIMG1_REG_OFFSET(TIMG_WDTWPROTECT_REG(1))
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#define TIMG1_INT_CLR_OFFSET TIMG1_REG_OFFSET(TIMG_INT_CLR_TIMERS_REG(1))
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#define TIMG1_WDT_STG0_HOLD_OFFSET TIMG1_REG_OFFSET(TIMG_WDTCONFIG2_REG(1))
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#define TIMG1_WDT_STG1_HOLD_OFFSET TIMG1_REG_OFFSET(TIMG_WDTCONFIG3_REG(1))
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#define TIMG1_WDT_FEED_OFFSET TIMG1_REG_OFFSET(TIMG_WDTFEED_REG(1))
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2020-12-24 08:30:36 -05:00
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#define UART0_DATA_REG (0x3FF40078)
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2021-09-01 09:55:50 -04:00
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.macro wdt_clr_intr_status dev
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movi a2, \dev
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movi a3, TIMG_WDT_WKEY_VALUE
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s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* disable write protect */
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memw
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l32i a4, a2, TIMG1_INT_CLR_OFFSET
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memw
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movi a3, 4
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or a3, a4, a3
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s32i a3, a2, TIMG1_INT_CLR_OFFSET /* clear 1st stage timeout interrupt */
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memw
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movi a3, 0
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s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* enable write protect */
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memw
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.endm
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.macro wdt_feed dev
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movi a2, \dev
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movi a3, TIMG_WDT_WKEY_VALUE
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s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* disable write protect */
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memw
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2021-09-02 09:10:29 -04:00
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movi a4, _lx_intr_livelock_max
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2021-09-01 09:55:50 -04:00
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l32i a4, a4, 0
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memw
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addi a4, a4, 1
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movi a3, (CONFIG_ESP_INT_WDT_TIMEOUT_MS<<1)
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quou a3, a3, a4
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s32i a3, a2, TIMG1_WDT_STG0_HOLD_OFFSET /* set timeout before interrupt */
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memw
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movi a3, (CONFIG_ESP_INT_WDT_TIMEOUT_MS<<2)
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s32i a3, a2, TIMG1_WDT_STG1_HOLD_OFFSET /* set timeout before system reset */
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memw
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movi a3, 1
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s32i a3, a2, TIMG1_WDT_FEED_OFFSET /* feed wdt */
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memw
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movi a3, 0
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s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* enable write protect */
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memw
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.endm
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.macro get_int_status_tg1wdt reg
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rsr \reg, INTERRUPT
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extui \reg, \reg, ETS_T1_WDT_CACHEERR_INUM, 1
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2020-12-24 08:30:36 -05:00
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beqz \reg, 99f /* not ETS_T1_WDT_INUM or ETS_CACHEERR_INUM */
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2021-09-01 09:55:50 -04:00
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getcoreid \reg
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bnez \reg, 98f
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2020-12-24 08:30:36 -05:00
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/* core 0 */
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movi \reg, UART0_DATA_REG
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l32i \reg, \reg, 0 /* Workaround for DPORT read error, for silicon revision 0~2 (ECO V0 ~ ECO V2). */
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2021-09-01 09:55:50 -04:00
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movi \reg, DPORT_PRO_INTR_STATUS_0_REG
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l32i \reg, \reg, 0
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2020-12-24 08:30:36 -05:00
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extui \reg, \reg, ETS_TG1_WDT_LEVEL_INTR_SOURCE, 1
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2021-09-01 09:55:50 -04:00
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j 99f
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2020-12-24 08:30:36 -05:00
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98: /* core 1 */
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movi \reg, UART0_DATA_REG
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l32i \reg, \reg, 0 /* Workaround for DPORT read error, for silicon revision 0~2 (ECO V0 ~ ECO V2). */
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2021-09-01 09:55:50 -04:00
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movi \reg, DPORT_APP_INTR_STATUS_0_REG
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l32i \reg, \reg, 0
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2020-12-24 08:30:36 -05:00
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extui \reg, \reg, ETS_TG1_WDT_LEVEL_INTR_SOURCE, 1
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2021-09-01 09:55:50 -04:00
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99:
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.endm
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2017-05-26 05:41:18 -04:00
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.data
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2021-09-02 09:10:29 -04:00
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_lx_intr_stack:
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.space LX_INTR_STACK_SIZE*portNUM_PROCESSORS /* This allocates stacks for each individual CPU. */
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2020-05-29 02:53:30 -04:00
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2020-06-24 00:05:12 -04:00
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT
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2021-09-02 09:10:29 -04:00
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.global _lx_intr_livelock_counter
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.global _lx_intr_livelock_max
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2020-05-29 02:53:30 -04:00
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.align 16
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2021-09-02 09:10:29 -04:00
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_lx_intr_livelock_counter:
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2020-05-29 02:53:30 -04:00
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.word 0
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2021-09-02 09:10:29 -04:00
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_lx_intr_livelock_max:
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2020-05-29 02:53:30 -04:00
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.word 0
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2021-09-02 09:10:29 -04:00
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_lx_intr_livelock_sync:
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2020-05-29 02:53:30 -04:00
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.word 0, 0
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2021-09-02 09:10:29 -04:00
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_lx_intr_livelock_app:
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2020-05-29 02:53:30 -04:00
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.word 0
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2021-09-02 09:10:29 -04:00
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_lx_intr_livelock_pro:
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2020-05-29 02:53:30 -04:00
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.word 0
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#endif
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2017-05-26 05:41:18 -04:00
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2017-04-18 05:14:32 -04:00
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.section .iram1,"ax"
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2021-09-02 09:10:29 -04:00
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.global xt_highintx
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.type xt_highintx,@function
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2017-04-18 05:14:32 -04:00
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.align 4
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xt_highintx:
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2017-04-18 05:14:32 -04:00
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2017-09-21 23:54:51 -04:00
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#ifndef CONFIG_FREERTOS_UNICORE
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2021-08-03 02:35:29 -04:00
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/* See if we're here for the IPC_ISR interrupt */
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2017-05-26 05:41:18 -04:00
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rsr a0, INTERRUPT
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2021-08-03 02:35:29 -04:00
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extui a0, a0, ETS_IPC_ISR_INUM, 1
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2020-12-24 08:30:36 -05:00
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beqz a0, 1f
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2021-09-13 07:20:51 -04:00
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/* Jump to `esp_ipc_isr_handler` which is non-returning. We need to use `jx`
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* because on Xtensa, `j` instruction can only refer to a label which
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* is in the range [-131068;+131075]. If the destination is out of scope,
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* linking will fail. So, to make sure we will always be able to jump to
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* that subroutine, retrieve its address and store it in a register. */
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movi a0, esp_ipc_isr_handler
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jx a0
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2020-12-24 08:30:36 -05:00
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1:
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#endif /* not CONFIG_FREERTOS_UNICORE */
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2021-09-01 09:55:50 -04:00
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2020-06-24 00:05:12 -04:00
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT
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2020-12-24 08:30:36 -05:00
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#if CONFIG_BTDM_CTRL_HLI
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2021-09-02 08:54:21 -04:00
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/* Timer 2 interrupt */
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rsr a0, INTENABLE
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extui a0, a0, 16, 1
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beqz a0, 1f
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rsr a0, INTERRUPT
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extui a0, a0, 16, 1
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bnez a0, .handle_multicore_debug_int
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1:
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2020-12-24 08:30:36 -05:00
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#endif /* CONFIG_BTDM_CTRL_HLI */
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/* ETS_T1_WDT_INUM */
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2021-09-02 09:10:29 -04:00
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#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
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2021-09-01 09:55:50 -04:00
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get_int_status_tg1wdt a0
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2021-09-02 09:10:29 -04:00
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#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
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/* See if we're here for the tg1 watchdog interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_T1_WDT_INUM, 1
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#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
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2020-05-29 02:53:30 -04:00
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beqz a0, 1f
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wsr a5, depc /* use DEPC as temp storage */
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2021-09-02 09:10:29 -04:00
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movi a0, _lx_intr_livelock_counter
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2020-05-29 02:53:30 -04:00
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l32i a0, a0, 0
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2021-09-02 09:10:29 -04:00
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movi a5, _lx_intr_livelock_max
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2020-05-29 02:53:30 -04:00
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l32i a5, a5, 0
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2021-09-02 09:10:29 -04:00
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bltu a0, a5, .handle_livelock_int /* _lx_intr_livelock_counter < _lx_intr_livelock_max */
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2020-05-29 02:53:30 -04:00
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rsr a5, depc /* restore a5 */
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#endif
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2020-12-24 08:30:36 -05:00
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1: /* ETS_CACHEERR_INUM or ETS_T1_WDT_INUM */
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2017-04-18 05:14:32 -04:00
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/* Allocate exception frame and save minimal context. */
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2021-09-01 09:55:50 -04:00
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mov a0, sp
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2017-04-18 05:14:32 -04:00
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, PS /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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2021-09-02 09:10:29 -04:00
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rsr a0, EPC_X /* save interruptee's PC */
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2017-04-18 05:14:32 -04:00
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s32i a0, sp, XT_STK_PC
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2022-02-03 03:54:23 -05:00
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rsr a0, EXCSAVE_X /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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2017-04-18 05:14:32 -04:00
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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call0 _xt_context_save
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/* Save vaddr into exception frame */
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rsr a0, EXCVADDR
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s32i a0, sp, XT_STK_EXCVADDR
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/* Figure out reason, save into EXCCAUSE reg */
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2021-09-02 09:10:29 -04:00
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#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
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2021-09-01 09:55:50 -04:00
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get_int_status_tg1wdt a0
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bnez a0, 1f
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/* TODO: Clear the MEMACCESS_ERR interrupt status. */
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2021-09-02 09:10:29 -04:00
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#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
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rsr a0, INTERRUPT
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extui a0, a0, ETS_MEMACCESS_ERR_INUM, 1 /* get cacheerr int bit */
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beqz a0, 1f
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#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
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2021-09-01 09:55:50 -04:00
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2017-04-18 05:14:32 -04:00
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/* Kill this interrupt; we cannot reset it. */
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rsr a0, INTENABLE
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2020-03-10 11:46:10 -04:00
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movi a4, ~(1<<ETS_MEMACCESS_ERR_INUM)
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2017-04-18 05:14:32 -04:00
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and a0, a4, a0
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wsr a0, INTENABLE
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movi a0, PANIC_RSN_CACHEERR
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j 9f
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1:
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2021-09-02 09:10:29 -04:00
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#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
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2021-09-01 09:55:50 -04:00
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/* Clear the WDT interrupt status. */
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wdt_clr_intr_status TIMERG1
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2021-09-02 09:10:29 -04:00
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#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
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2019-04-30 06:51:55 -04:00
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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2017-04-18 05:14:32 -04:00
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/* Check if the cause is the app cpu failing to tick.*/
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movi a0, int_wdt_app_cpu_ticked
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
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movi a0,PANIC_RSN_INTWDT_CPU1
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j 9f
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2:
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#endif
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/* Set EXCCAUSE to reflect cause of the wdt int trigger */
|
|
|
|
movi a0,PANIC_RSN_INTWDT_CPU0
|
|
|
|
9:
|
|
|
|
/* Found the reason, now save it. */
|
|
|
|
s32i a0, sp, XT_STK_EXCCAUSE
|
|
|
|
|
|
|
|
/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
|
|
|
|
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
|
|
|
|
wsr a0, PS
|
|
|
|
|
2020-12-24 08:30:36 -05:00
|
|
|
/* Call panic handler */
|
2017-04-18 05:14:32 -04:00
|
|
|
mov a6,sp
|
|
|
|
call4 panicHandler
|
|
|
|
|
|
|
|
call0 _xt_context_restore
|
|
|
|
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
|
|
|
|
wsr a0, PS
|
|
|
|
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
|
2021-09-02 09:10:29 -04:00
|
|
|
wsr a0, EPC_X
|
2017-04-18 05:14:32 -04:00
|
|
|
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
|
|
|
|
l32i sp, sp, XT_STK_A1 /* remove exception frame */
|
|
|
|
rsync /* ensure PS and EPC written */
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
rsr a0, EXCSAVE_X /* restore a0 */
|
|
|
|
rfi RFI_X
|
2017-04-18 05:14:32 -04:00
|
|
|
|
|
|
|
|
2020-06-24 00:05:12 -04:00
|
|
|
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT
|
2020-12-24 08:30:36 -05:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-02 08:54:21 -04:00
|
|
|
#define APB_ITCTRL (0x3f00)
|
|
|
|
#define APB_DCRSET (0x200c)
|
|
|
|
|
|
|
|
#define ERI_ADDR(APB) (0x100000 + (APB))
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
.handle_multicore_debug_int:
|
|
|
|
|
|
|
|
wsr a2, depc /* temp storage */
|
|
|
|
|
|
|
|
rsr.ccount a2
|
2022-03-02 02:49:31 -05:00
|
|
|
addmi a2, a2, (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ*50)
|
2021-09-02 08:54:21 -04:00
|
|
|
wsr a2, CCOMPARE2
|
|
|
|
|
|
|
|
/* Enable Integration Mode */
|
|
|
|
movi a2, ERI_ADDR(APB_ITCTRL)
|
|
|
|
rer a0, a2
|
|
|
|
addi a0, a0, 1
|
|
|
|
wer a0, a2
|
|
|
|
|
|
|
|
/* Enable and emit BreakOut signal */
|
|
|
|
movi a2, ERI_ADDR(APB_DCRSET)
|
|
|
|
rer a0, a2
|
|
|
|
movi a2, 0x1020000
|
|
|
|
or a0, a2, a0
|
|
|
|
movi a2, ERI_ADDR(APB_DCRSET)
|
|
|
|
wer a0, a2
|
|
|
|
|
|
|
|
.rept 4
|
|
|
|
nop
|
|
|
|
.endr
|
|
|
|
|
2020-12-24 08:30:36 -05:00
|
|
|
/* Enable Normal Mode */
|
2021-09-02 08:54:21 -04:00
|
|
|
movi a2, ERI_ADDR(APB_ITCTRL)
|
|
|
|
rer a0, a2
|
|
|
|
movi a2, ~0x1
|
|
|
|
and a0, a2, a0
|
|
|
|
movi a2, ERI_ADDR(APB_ITCTRL)
|
|
|
|
wer a0, a2
|
|
|
|
|
|
|
|
rsr a2, depc
|
|
|
|
|
2020-12-24 08:30:36 -05:00
|
|
|
rsr a0, EXCSAVE_5 /* restore a0 */
|
2021-09-02 08:54:21 -04:00
|
|
|
rfi 5
|
2020-12-24 08:30:36 -05:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2020-05-29 02:53:30 -04:00
|
|
|
|
|
|
|
/*
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Macro intr_matrix_map - Attach an CPU interrupt to a hardware source.
|
|
|
|
|
|
|
|
Input : "addr" - Interrupt map configuration base address
|
|
|
|
Input : "src" - Interrupt source.
|
|
|
|
Input : "inum" - Interrupt number.
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
*/
|
|
|
|
.macro intr_matrix_map addr src inum
|
|
|
|
movi a2, \src
|
|
|
|
slli a2, a2, 2
|
|
|
|
movi a3, \addr
|
|
|
|
add a3, a3, a2
|
|
|
|
movi a2, \inum
|
|
|
|
s32i a2, a3, 0
|
|
|
|
memw
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
.handle_livelock_int:
|
|
|
|
|
|
|
|
getcoreid a5
|
|
|
|
|
|
|
|
/* Save A2, A3, A4 so we can use those registers */
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a0, LX_INTR_STACK_SIZE
|
2020-05-29 02:53:30 -04:00
|
|
|
mull a5, a5, a0
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a0, _lx_intr_stack
|
2020-05-29 02:53:30 -04:00
|
|
|
add a0, a0, a5
|
2021-09-02 09:10:29 -04:00
|
|
|
s32i a2, a0, LX_INTR_A2_OFFSET
|
|
|
|
s32i a3, a0, LX_INTR_A3_OFFSET
|
|
|
|
s32i a4, a0, LX_INTR_A4_OFFSET
|
2020-05-29 02:53:30 -04:00
|
|
|
|
|
|
|
/* Here, we can use a0, a2, a3, a4, a5 registers */
|
|
|
|
getcoreid a5
|
|
|
|
|
|
|
|
rsil a0, CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL /* disable nested interrupt */
|
|
|
|
|
|
|
|
beqz a5, 1f
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_app
|
2020-05-29 02:53:30 -04:00
|
|
|
l32i a3, a2, 0
|
|
|
|
addi a3, a3, 1
|
|
|
|
s32i a3, a2, 0
|
|
|
|
|
|
|
|
/* Dual core synchronization, ensuring that both cores enter interrupts */
|
|
|
|
1: movi a4, 0x1
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_sync
|
2020-05-29 02:53:30 -04:00
|
|
|
addx4 a3, a5, a2
|
|
|
|
s32i a4, a3, 0
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
1: movi a2, _lx_intr_livelock_sync
|
2020-05-29 02:53:30 -04:00
|
|
|
movi a3, 1
|
|
|
|
addx4 a3, a3, a2
|
|
|
|
l32i a2, a2, 0
|
|
|
|
l32i a3, a3, 0
|
|
|
|
and a2, a2, a3
|
|
|
|
beqz a2, 1b
|
|
|
|
|
|
|
|
beqz a5, 1f /* Pro cpu (Core 0) jump bypass */
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_app
|
2020-05-29 02:53:30 -04:00
|
|
|
l32i a2, a2, 0
|
|
|
|
bnei a2, 2, 1f
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_counter /* _lx_intr_livelock_counter++ */
|
2020-05-29 02:53:30 -04:00
|
|
|
l32i a3, a2, 0
|
|
|
|
addi a3, a3, 1
|
|
|
|
s32i a3, a2, 0
|
|
|
|
|
|
|
|
/*
|
|
|
|
The delay time can be calculated by the following formula:
|
|
|
|
T = ceil(0.25 + max(t1, t2)) us
|
|
|
|
|
|
|
|
t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2
|
|
|
|
|
|
|
|
f1: PSRAM access frequency, unit: MHz.
|
|
|
|
f2: Flash access frequency, unit: MHz.
|
|
|
|
|
|
|
|
When flash is slow/fast read, N = 1.
|
|
|
|
When flash is DOUT/DIO read, N = 2.
|
|
|
|
When flash is QOUT/QIO read, N = 4.
|
|
|
|
*/
|
|
|
|
1: rsr.ccount a2
|
|
|
|
#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
|
|
|
|
# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
|
|
|
|
movi a3, 480
|
|
|
|
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
|
|
|
|
movi a3, 720
|
|
|
|
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
|
|
|
|
movi a3, 720
|
|
|
|
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
|
|
|
|
movi a3, 960
|
|
|
|
# else
|
|
|
|
movi a3, 1200
|
|
|
|
# endif
|
|
|
|
#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
|
|
|
|
# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
|
|
|
|
movi a3, 720
|
|
|
|
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
|
|
|
|
movi a3, 720
|
|
|
|
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
|
|
|
|
movi a3, 1200
|
|
|
|
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
|
|
|
|
movi a3, 1680
|
|
|
|
# else
|
|
|
|
movi a3, 2160
|
|
|
|
# endif
|
|
|
|
#endif
|
|
|
|
2: rsr.ccount a4 /* delay_us(N) */
|
|
|
|
sub a4, a4, a2
|
|
|
|
bltu a4, a3, 2b
|
|
|
|
|
|
|
|
beqz a5, 2f
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_app
|
2020-05-29 02:53:30 -04:00
|
|
|
l32i a2, a2, 0
|
|
|
|
beqi a2, 2, 8f
|
|
|
|
j 3f
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
2: movi a2, _lx_intr_livelock_pro
|
2020-05-29 02:53:30 -04:00
|
|
|
l32i a4, a2, 0
|
|
|
|
addi a4, a4, 1
|
|
|
|
s32i a4, a2, 0
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_sync
|
2020-05-29 02:53:30 -04:00
|
|
|
movi a3, 1
|
|
|
|
addx4 a3, a3, a2
|
|
|
|
l32i a2, a2, 0
|
|
|
|
l32i a3, a3, 0
|
|
|
|
and a2, a2, a3
|
|
|
|
beqz a2, 5f
|
|
|
|
j 1b
|
|
|
|
5: bgei a4, 2, 4f
|
|
|
|
j 1b
|
|
|
|
|
|
|
|
/*
|
|
|
|
Pro cpu (Core 0) jump bypass, continue waiting, App cpu (Core 1)
|
|
|
|
can execute to here, unmap itself tg1 1st stage timeout interrupt
|
2021-09-02 09:10:29 -04:00
|
|
|
then restore registers and exit highint5/4.
|
2020-05-29 02:53:30 -04:00
|
|
|
*/
|
|
|
|
3: intr_matrix_map DPORT_APP_MAC_INTR_MAP_REG, ETS_TG1_WDT_LEVEL_INTR_SOURCE, 16
|
|
|
|
j 9f
|
|
|
|
|
|
|
|
/*
|
|
|
|
Here, App cpu (Core 1) has exited isr, Pro cpu (Core 0) help the
|
|
|
|
App cpu map tg1 1st stage timeout interrupt clear tg1 interrupt.
|
|
|
|
*/
|
|
|
|
4: intr_matrix_map DPORT_APP_MAC_INTR_MAP_REG, ETS_TG1_WDT_LEVEL_INTR_SOURCE, ETS_T1_WDT_INUM
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
1: movi a2, _lx_intr_livelock_sync
|
2020-05-29 02:53:30 -04:00
|
|
|
movi a4, 1
|
|
|
|
addx4 a3, a4, a2
|
|
|
|
l32i a2, a2, 0
|
|
|
|
l32i a3, a3, 0
|
|
|
|
and a2, a2, a3
|
2021-09-02 09:10:29 -04:00
|
|
|
beqz a2, 1b /* Wait for App cpu to enter highint5/4 again */
|
2020-05-29 02:53:30 -04:00
|
|
|
|
|
|
|
wdt_clr_intr_status TIMERG1
|
|
|
|
j 9f
|
|
|
|
|
|
|
|
/* Feed watchdog */
|
|
|
|
8: wdt_feed TIMERG1
|
|
|
|
|
2021-08-03 02:35:29 -04:00
|
|
|
9: wsr a0, PS /* restore interrupt level */
|
2020-05-29 02:53:30 -04:00
|
|
|
|
|
|
|
movi a0, 0
|
|
|
|
beqz a5, 1f
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_app
|
2020-05-29 02:53:30 -04:00
|
|
|
l32i a3, a2, 0
|
|
|
|
bnei a3, 2, 1f
|
|
|
|
s32i a0, a2, 0
|
|
|
|
|
|
|
|
1: bnez a5, 2f
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a2, _lx_intr_livelock_pro
|
2020-05-29 02:53:30 -04:00
|
|
|
s32i a0, a2, 0
|
2021-09-02 09:10:29 -04:00
|
|
|
2: movi a2, _lx_intr_livelock_sync
|
2020-05-29 02:53:30 -04:00
|
|
|
addx4 a2, a5, a2
|
|
|
|
s32i a0, a2, 0
|
|
|
|
|
|
|
|
/* Done. Restore registers and return. */
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a0, LX_INTR_STACK_SIZE
|
2020-05-29 02:53:30 -04:00
|
|
|
mull a5, a5, a0
|
2021-09-02 09:10:29 -04:00
|
|
|
movi a0, _lx_intr_stack
|
2020-05-29 02:53:30 -04:00
|
|
|
add a0, a0, a5
|
2021-09-02 09:10:29 -04:00
|
|
|
l32i a2, a0, LX_INTR_A2_OFFSET
|
|
|
|
l32i a3, a0, LX_INTR_A3_OFFSET
|
|
|
|
l32i a4, a0, LX_INTR_A4_OFFSET
|
2020-05-29 02:53:30 -04:00
|
|
|
rsync /* ensure register restored */
|
|
|
|
|
|
|
|
rsr a5, depc
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
rsr a0, EXCSAVE_X /* restore a0 */
|
|
|
|
rfi RFI_X
|
2020-05-29 02:53:30 -04:00
|
|
|
|
|
|
|
#endif
|
2017-04-18 05:14:32 -04:00
|
|
|
|
|
|
|
/* The linker has no reason to link in this file; all symbols it exports are already defined
|
2019-03-26 04:30:43 -04:00
|
|
|
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
|
2017-04-18 05:14:32 -04:00
|
|
|
linker inspect this anyway. */
|
|
|
|
|
2021-08-03 02:35:29 -04:00
|
|
|
.global ld_include_highint_hdl
|
|
|
|
ld_include_highint_hdl:
|