alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity
116197040f
esp-idf/components/soc/esp32s3/include/soc/assist_debug_struct.h

467 lines
17 KiB
C
Raw Normal View History

soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
#define _SOC_ASSIST_DEBUG_STRUCT_H_
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
#include <stdint.h>
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
#ifdef __cplusplus
extern "C" {
#endif
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one update all struct headers to be more "standardized": - bit fields are properly wrapped with struct - bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits - bit field should be uint32_t - typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199 added helper macros to force peripheral registers being accessed in 32 bitwidth added a check script into ci
2021-08-23 02:03:23 -04:00
typedef volatile struct assist_debug_dev_s {
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_area_dram0_0_rd : 1;
uint32_t core_0_area_dram0_0_wr : 1;
uint32_t core_0_area_dram0_1_rd : 1;
uint32_t core_0_area_dram0_1_wr : 1;
uint32_t core_0_area_pif_0_rd : 1;
uint32_t core_0_area_pif_0_wr : 1;
uint32_t core_0_area_pif_1_rd : 1;
uint32_t core_0_area_pif_1_wr : 1;
uint32_t core_0_sp_spill_min : 1;
uint32_t core_0_sp_spill_max : 1;
uint32_t core_0_iram0_exception_monitor: 1;
uint32_t core_0_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_interrupt_ena;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_area_dram0_0_rd : 1;
uint32_t core_0_area_dram0_0_wr : 1;
uint32_t core_0_area_dram0_1_rd : 1;
uint32_t core_0_area_dram0_1_wr : 1;
uint32_t core_0_area_pif_0_rd : 1;
uint32_t core_0_area_pif_0_wr : 1;
uint32_t core_0_area_pif_1_rd : 1;
uint32_t core_0_area_pif_1_wr : 1;
uint32_t core_0_sp_spill_min : 1;
uint32_t core_0_sp_spill_max : 1;
uint32_t core_0_iram0_exception_monitor: 1;
uint32_t core_0_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_interrupt_raw;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_area_dram0_0_rd : 1;
uint32_t core_0_area_dram0_0_wr : 1;
uint32_t core_0_area_dram0_1_rd : 1;
uint32_t core_0_area_dram0_1_wr : 1;
uint32_t core_0_area_pif_0_rd : 1;
uint32_t core_0_area_pif_0_wr : 1;
uint32_t core_0_area_pif_1_rd : 1;
uint32_t core_0_area_pif_1_wr : 1;
uint32_t core_0_sp_spill_min : 1;
uint32_t core_0_sp_spill_max : 1;
uint32_t core_0_iram0_exception_monitor: 1;
uint32_t core_0_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_interrupt_rls;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_area_dram0_0_rd : 1;
uint32_t core_0_area_dram0_0_wr : 1;
uint32_t core_0_area_dram0_1_rd : 1;
uint32_t core_0_area_dram0_1_wr : 1;
uint32_t core_0_area_pif_0_rd : 1;
uint32_t core_0_area_pif_0_wr : 1;
uint32_t core_0_area_pif_1_rd : 1;
uint32_t core_0_area_pif_1_wr : 1;
uint32_t core_0_sp_spill_min : 1;
uint32_t core_0_sp_spill_max : 1;
uint32_t core_0_iram0_exception_monitor: 1;
uint32_t core_0_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_interrupt_clr;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_area_dram0_0_min;
uint32_t core_0_area_dram0_0_max;
uint32_t core_0_area_dram0_1_min;
uint32_t core_0_area_dram0_1_max;
uint32_t core_0_area_pif_0_min;
uint32_t core_0_area_pif_0_max;
uint32_t core_0_area_pif_1_min;
uint32_t core_0_area_pif_1_max;
uint32_t core_0_area_sp;
uint32_t core_0_area_pc;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_sp_unstable : 8;
uint32_t reserved8 : 24;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_sp_unstable;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_sp_min;
uint32_t core_0_sp_max;
uint32_t core_0_sp_pc;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_rcd_pdebugenable : 1;
uint32_t reserved1 : 31;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_rcd_pdebugenable;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_rcd_recording : 1;
uint32_t reserved1 : 31;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_rcd_recording;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_rcd_pdebuginst;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_rcd_pdebugstatus : 8;
uint32_t reserved8 : 24;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_rcd_pdebugstatus;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_rcd_pdebugdata;
uint32_t core_0_rcd_pdebugpc;
uint32_t core_0_rcd_pdebugls0stat;
uint32_t core_0_rcd_pdebugls0addr;
uint32_t core_0_rcd_pdebugls0data;
uint32_t core_0_rcd_sp;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_iram0_recording_addr_0 : 24;
uint32_t core_0_iram0_recording_wr_0 : 1;
uint32_t core_0_iram0_recording_loadstore_0: 1;
uint32_t reserved26 : 6;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_iram0_exception_monitor_0;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_iram0_recording_addr_1 : 24;
uint32_t core_0_iram0_recording_wr_1 : 1;
uint32_t core_0_iram0_recording_loadstore_1: 1;
uint32_t reserved26 : 6;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_iram0_exception_monitor_1;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_dram0_recording_addr_0 : 22;
uint32_t core_0_dram0_recording_wr_0 : 1;
uint32_t reserved23 : 9;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_dram0_exception_monitor_0;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_dram0_recording_byteen_0: 16;
uint32_t reserved16 : 16;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_dram0_exception_monitor_1;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_dram0_exception_monitor_2;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_dram0_recording_addr_1 : 22;
uint32_t core_0_dram0_recording_wr_1 : 1;
uint32_t reserved23 : 9;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_dram0_exception_monitor_3;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_dram0_recording_byteen_1: 16;
uint32_t reserved16 : 16;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_0_dram0_exception_monitor_4;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_0_dram0_exception_monitor_5;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_area_dram0_0_rd : 1;
uint32_t core_1_area_dram0_0_wr : 1;
uint32_t core_1_area_dram0_1_rd : 1;
uint32_t core_1_area_dram0_1_wr : 1;
uint32_t core_1_area_pif_0_rd : 1;
uint32_t core_1_area_pif_0_wr : 1;
uint32_t core_1_area_pif_1_rd : 1;
uint32_t core_1_area_pif_1_wr : 1;
uint32_t core_1_sp_spill_min : 1;
uint32_t core_1_sp_spill_max : 1;
uint32_t core_1_iram0_exception_monitor: 1;
uint32_t core_1_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_interrupt_ena;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_area_dram0_0_rd : 1;
uint32_t core_1_area_dram0_0_wr : 1;
uint32_t core_1_area_dram0_1_rd : 1;
uint32_t core_1_area_dram0_1_wr : 1;
uint32_t core_1_area_pif_0_rd : 1;
uint32_t core_1_area_pif_0_wr : 1;
uint32_t core_1_area_pif_1_rd : 1;
uint32_t core_1_area_pif_1_wr : 1;
uint32_t core_1_sp_spill_min : 1;
uint32_t core_1_sp_spill_max : 1;
uint32_t core_1_iram0_exception_monitor: 1;
uint32_t core_1_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_interrupt_raw;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_area_dram0_0_rd : 1;
uint32_t core_1_area_dram0_0_wr : 1;
uint32_t core_1_area_dram0_1_rd : 1;
uint32_t core_1_area_dram0_1_wr : 1;
uint32_t core_1_area_pif_0_rd : 1;
uint32_t core_1_area_pif_0_wr : 1;
uint32_t core_1_area_pif_1_rd : 1;
uint32_t core_1_area_pif_1_wr : 1;
uint32_t core_1_sp_spill_min : 1;
uint32_t core_1_sp_spill_max : 1;
uint32_t core_1_iram0_exception_monitor: 1;
uint32_t core_1_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_interrupt_rls;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_area_dram0_0_rd : 1;
uint32_t core_1_area_dram0_0_wr : 1;
uint32_t core_1_area_dram0_1_rd : 1;
uint32_t core_1_area_dram0_1_wr : 1;
uint32_t core_1_area_pif_0_rd : 1;
uint32_t core_1_area_pif_0_wr : 1;
uint32_t core_1_area_pif_1_rd : 1;
uint32_t core_1_area_pif_1_wr : 1;
uint32_t core_1_sp_spill_min : 1;
uint32_t core_1_sp_spill_max : 1;
uint32_t core_1_iram0_exception_monitor: 1;
uint32_t core_1_dram0_exception_monitor: 1;
uint32_t reserved12 : 20;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_interrupt_clr;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_area_dram0_0_min;
uint32_t core_1_area_dram0_0_max;
uint32_t core_1_area_dram0_1_min;
uint32_t core_1_area_dram0_1_max;
uint32_t core_1_area_pif_0_min;
uint32_t core_1_area_pif_0_max;
uint32_t core_1_area_pif_1_min;
uint32_t core_1_area_pif_1_max;
uint32_t core_1_area_pc;
uint32_t core_1_area_sp;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_sp_unstable : 8;
uint32_t reserved8 : 24;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_sp_unstable;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_sp_min;
uint32_t core_1_sp_max;
uint32_t core_1_sp_pc;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_rcd_pdebugenable : 1;
uint32_t reserved1 : 31;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_rcd_pdebugenable;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_rcd_recording : 1;
uint32_t reserved1 : 31;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_rcd_recording;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_rcd_pdebuginst;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_rcd_pdebugstatus : 8;
uint32_t reserved8 : 24;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_rcd_pdebugstatus;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_rcd_pdebugdata;
uint32_t core_1_rcd_pdebugpc;
uint32_t core_1_rcd_pdebugls0stat;
uint32_t core_1_rcd_pdebugls0addr;
uint32_t core_1_rcd_pdebugls0data;
uint32_t core_1_rcd_sp;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_iram0_recording_addr_0 : 24;
uint32_t core_1_iram0_recording_wr_0 : 1;
uint32_t core_1_iram0_recording_loadstore_0: 1;
uint32_t reserved26 : 6;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_iram0_exception_monitor_0;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_iram0_recording_addr_1 : 24;
uint32_t core_1_iram0_recording_wr_1 : 1;
uint32_t core_1_iram0_recording_loadstore_1: 1;
uint32_t reserved26 : 6;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_iram0_exception_monitor_1;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_dram0_recording_addr_0 : 22;
uint32_t core_1_dram0_recording_wr_0 : 1;
uint32_t reserved23 : 9;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_dram0_exception_monitor_0;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_dram0_recording_byteen_0: 16;
uint32_t reserved16 : 16;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_dram0_exception_monitor_1;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_dram0_exception_monitor_2;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_dram0_recording_addr_1 : 22;
uint32_t core_1_dram0_recording_wr_1 : 1;
uint32_t reserved23 : 9;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_dram0_exception_monitor_3;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_dram0_recording_byteen_1: 16;
uint32_t reserved16 : 16;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_1_dram0_exception_monitor_4;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_1_dram0_exception_monitor_5;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
uint32_t reserved20 : 12;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_x_iram0_dram0_exception_monitor_0;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
uint32_t reserved20 : 12;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} core_x_iram0_dram0_exception_monitor_1;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t log : 3;
uint32_t log_mode : 3;
uint32_t log_mem_loopble : 1;
uint32_t reserved7 : 25;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} log_setting;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t log_data_0;
uint32_t log_data_1;
uint32_t log_data_2;
uint32_t log_data_3;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t log_data_size : 16;
uint32_t reserved16 : 16;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} log_data_mask;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t log_min;
uint32_t log_max;
uint32_t log_mem_start;
uint32_t log_mem_end;
uint32_t log_mem_writing_addr;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t log_mem_full_flag : 1;
uint32_t reserved1 : 31;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
} log_mem_full_flag;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
uint32_t assist_debug_reg_date : 28;
uint32_t reserved28 : 4;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
};
uint32_t val;
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
} reg_date;
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
} assist_debug_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
#ifdef __cplusplus
}
#endif
soc: update the csv headers for esp32s3
2021-06-09 06:42:54 -04:00
#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */
Reference in New Issue Copy Permalink