2022-12-28 02:04:51 -05:00
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2024-04-15 02:12:47 -04:00
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#include "soc/clkout_channel.h"
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#include "hal/assert.h"
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2022-12-28 02:04:51 -05:00
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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2024-04-15 02:12:47 -04:00
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#include "hal/gpio_ll.h"
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2022-12-28 02:04:51 -05:00
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#include "hal/log.h"
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static const char *CLK_HAL_TAG = "clk_hal";
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_PLL:
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return clk_ll_bbpll_get_freq_mhz();
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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case SOC_CPU_CLK_SRC_APLL:
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return clk_hal_apll_get_freq_hz() / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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switch (source) {
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case SOC_CPU_CLK_SRC_PLL:
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return clk_ll_cpu_get_freq_mhz_from_pll() * MHZ;
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case SOC_CPU_CLK_SRC_APLL: {
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uint32_t apll_freq_hz = clk_hal_apll_get_freq_hz();
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uint32_t divider = clk_ll_cpu_get_divider_from_apll();
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if (divider == 0) {
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HAL_LOGE(CLK_HAL_TAG, "Invalid cpu config");
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return 0;
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}
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return apll_freq_hz / divider;
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}
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default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / clk_ll_cpu_get_divider();
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}
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}
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2023-12-15 03:19:44 -05:00
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static uint32_t clk_hal_ahb_get_freq_hz(void)
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2022-12-28 02:04:51 -05:00
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{
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// AHB_CLK path is highly dependent on CPU_CLK path
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switch (clk_ll_cpu_get_src()) {
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case SOC_CPU_CLK_SRC_PLL:
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// AHB_CLK is a fixed value when CPU_CLK is clocked from PLL
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return CLK_LL_AHB_MAX_FREQ_MHZ * MHZ;
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case SOC_CPU_CLK_SRC_APLL:
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return clk_hal_cpu_get_freq_hz() >> 1;
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default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
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return clk_hal_cpu_get_freq_hz();
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}
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_ahb_get_freq_hz();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256:
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return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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uint32_t freq = clk_ll_xtal_load_freq_mhz();
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if (freq == 0) {
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2024-01-03 02:28:29 -05:00
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return (uint32_t)SOC_XTAL_FREQ_AUTO;
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2022-12-28 02:04:51 -05:00
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}
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return freq;
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}
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uint32_t clk_hal_apll_get_freq_hz(void)
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{
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2023-10-10 00:43:21 -04:00
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uint64_t xtal_freq_hz = (uint64_t)clk_hal_xtal_get_freq_mhz() * 1000000ULL;
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2022-12-28 02:04:51 -05:00
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uint32_t o_div = 0;
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uint32_t sdm0 = 0;
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uint32_t sdm1 = 0;
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uint32_t sdm2 = 0;
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clk_ll_apll_get_config(&o_div, &sdm0, &sdm1, &sdm2);
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2023-09-22 03:27:16 -04:00
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uint32_t numerator = ((4 + sdm2) << 16) | (sdm1 << 8) | sdm0;
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uint32_t denominator = (o_div + 2) << 17;
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uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator);
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2022-12-28 02:04:51 -05:00
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return apll_freq_hz;
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}
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2024-04-15 02:12:47 -04:00
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void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id)
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{
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gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
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}
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void clk_hal_clock_output_teardown(uint8_t channel_id)
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{
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gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
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}
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