esp-idf/components/freertos/component.mk

#
# Component Makefile
#

ifdef CONFIG_FREERTOS_DEBUG_OCDAWARE
	COMPONENT_ADD_LDFLAGS += -Wl,--undefined=uxTopUsedPriority
endif

COMPONENT_ADD_INCLUDEDIRS := include port/xtensa/include
COMPONENT_PRIV_INCLUDEDIRS := include/freertos port/xtensa/include/freertos port/xtensa port/priv_include .
COMPONENT_SRCDIRS += port port/xtensa

ifndef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
	COMPONENT_OBJEXCLUDE := xtensa/xtensa_loadstore_handler.o
endif

tasks.o event_groups.o timers.o queue.o: CFLAGS += -D_ESP_FREERTOS_INTERNAL
COMPONENT_ADD_LDFRAGMENTS += linker.lf
Initial public version 2016-08-17 11:08:22 -04:00			`#`
			`# Component Makefile`
			`#`

freertos: fix defining uxTopUsedPriority for esp32s2beta 2019-10-16 08:23:05 -04:00			`ifdef CONFIG_FREERTOS_DEBUG_OCDAWARE`
			`COMPONENT_ADD_LDFLAGS += -Wl,--undefined=uxTopUsedPriority`
			`endif`

freertos: Add RISC-V port Changes come from internal branch commit a6723fc 2020-11-05 23:03:21 -05:00			`COMPONENT_ADD_INCLUDEDIRS := include port/xtensa/include`
freertos(esp32s3): SysTick uses systimer 2021-08-04 08:33:44 -04:00			`COMPONENT_PRIV_INCLUDEDIRS := include/freertos port/xtensa/include/freertos port/xtensa port/priv_include .`
freertos: Add RISC-V port Changes come from internal branch commit a6723fc 2020-11-05 23:03:21 -05:00			`COMPONENT_SRCDIRS += port port/xtensa`
freertos: make task{ENTER/EXIT} macros deprecated for external use Signed-off-by: Mahavir Jain <mahavir@espressif.com> 2018-06-11 04:36:32 -04:00
Exception handlers for LoadStoreError and LoadStoreAlignmentError Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection. 2020-02-26 07:21:59 -05:00			`ifndef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY`
			`COMPONENT_OBJEXCLUDE := xtensa/xtensa_loadstore_handler.o`
			`endif`

esp_ringbuf: fix default placement from flash to IRAM In earlier change this component was decoupled from freertos and hence regression was introduced which changed default placement to flash. Some device drivers make use of ringbuffer while flash cache is being disabled and hence default placement should instead be internal memory. Closes: https://github.com/espressif/esp-idf/issues/2517 2018-10-09 07:56:14 -04:00			`tasks.o event_groups.o timers.o queue.o: CFLAGS += -D_ESP_FREERTOS_INTERNAL`
tools: implement linker script generation 2018-04-17 22:57:45 -04:00			`COMPONENT_ADD_LDFRAGMENTS += linker.lf`