2022-11-22 02:14:51 -05:00
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2022-12-06 00:46:03 -05:00
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2024-02-12 00:51:25 -05:00
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#include "ld.common"
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2022-12-06 00:46:03 -05:00
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/* Default entry point */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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/**
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* RTC fast memory holds RTC wake stub code,
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* including from any source file named rtc_wake_stub*.c
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*/
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.rtc.text :
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{
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. = ALIGN(4);
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_rtc_fast_start = ABSOLUTE(.);
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2023-07-03 08:36:39 -04:00
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_rtc_text_start = ABSOLUTE(.);
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*(.rtc.entry.text)
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2022-12-06 00:46:03 -05:00
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mapping[rtc_text]
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*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
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*(.rtc_text_end_test)
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/* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */
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. += _esp_memprot_prefetch_pad_size;
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. = ALIGN(4);
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_rtc_text_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section located in RTC FAST Memory area.
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* It holds data marked with RTC_FAST_ATTR attribute.
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* See the file "esp_attr.h" for more information.
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*/
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.rtc.force_fast :
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{
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. = ALIGN(4);
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_rtc_force_fast_start = ABSOLUTE(.);
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mapping[rtc_force_fast]
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*(.rtc.force_fast .rtc.force_fast.*)
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. = ALIGN(4) ;
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_rtc_force_fast_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* RTC data section holds RTC wake stub
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* data/rodata, including from any source file
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* named rtc_wake_stub*.c and the data marked with
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* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
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*/
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.rtc.data :
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{
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_rtc_data_start = ABSOLUTE(.);
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mapping[rtc_data]
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2023-01-04 00:39:18 -05:00
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*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
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2022-12-06 00:46:03 -05:00
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_rtc_data_end = ABSOLUTE(.);
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} > lp_ram_seg
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/* RTC bss, from any source file named rtc_wake_stub*.c */
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.rtc.bss (NOLOAD) :
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{
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_rtc_bss_start = ABSOLUTE(.);
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2023-01-04 00:39:18 -05:00
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*rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
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2022-12-06 00:46:03 -05:00
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*rtc_wake_stub*.*(COMMON)
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mapping[rtc_bss]
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_rtc_bss_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section holds data that should not be initialized at power up
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* and will be retained during deep sleep.
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* User data marked with RTC_NOINIT_ATTR will be placed
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* into this section. See the file "esp_attr.h" for more information.
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*/
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.rtc_noinit (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_noinit_start = ABSOLUTE(.);
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*(.rtc_noinit .rtc_noinit.*)
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. = ALIGN(4) ;
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_rtc_noinit_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section located in RTC SLOW Memory area.
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* It holds data marked with RTC_SLOW_ATTR attribute.
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* See the file "esp_attr.h" for more information.
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*/
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.rtc.force_slow :
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{
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. = ALIGN(4);
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_rtc_force_slow_start = ABSOLUTE(.);
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*(.rtc.force_slow .rtc.force_slow.*)
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. = ALIGN(4) ;
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_rtc_force_slow_end = ABSOLUTE(.);
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} > lp_ram_seg
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2023-03-31 12:41:40 -04:00
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/**
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* This section holds RTC data that should have fixed addresses.
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* The data are not initialized at power-up and are retained during deep sleep.
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*/
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.rtc_reserved (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_reserved_start = ABSOLUTE(.);
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/* New data can only be added here to ensure existing data are not moved.
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Because data have adhered to the end of the segment and code is relied on it.
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>> put new data here << */
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*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
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KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
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_rtc_reserved_end = ABSOLUTE(.);
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} > rtc_reserved_seg
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_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
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ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
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"RTC reserved segment data does not fit.")
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2022-12-06 00:46:03 -05:00
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/* Get size of rtc slow data based on rtc_data_location alias */
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_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_slow_end - _rtc_data_start)
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: (_rtc_force_slow_end - _rtc_force_slow_start);
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_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_fast_end - _rtc_fast_start)
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: (_rtc_noinit_end - _rtc_fast_start);
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ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
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"RTC_SLOW segment data does not fit.")
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ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
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"RTC_FAST segment data does not fit.")
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.iram0.text :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to start of IRAM */
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ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
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2023-08-14 03:44:24 -04:00
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KEEP(*(.exception_vectors_table.text));
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2022-12-06 00:46:03 -05:00
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KEEP(*(.exception_vectors.text));
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. = ALIGN(4);
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_invalid_pc_placeholder = ABSOLUTE(.);
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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mapping[iram0_text]
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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/* ESP32-H2 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
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. += _esp_memprot_prefetch_pad_size;
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. = ALIGN(_esp_memprot_align_size);
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/* iram_end_test section exists for use by memprot unit tests only */
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*(.iram_end_test)
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_iram_text_end = ABSOLUTE(.);
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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.iram0.data :
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{
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. = ALIGN(16);
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_iram_data_start = ABSOLUTE(.);
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mapping[iram0_data]
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_iram_data_end = ABSOLUTE(.);
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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.iram0.bss (NOLOAD) :
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{
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. = ALIGN(16);
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_iram_bss_start = ABSOLUTE(.);
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mapping[iram0_bss]
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_iram_bss_end = ABSOLUTE(.);
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. = ALIGN(16);
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_iram_end = ABSOLUTE(.);
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.gnu.linkonce.d.*)
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*(.data1)
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__global_pointer$ = . + 0x800;
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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mapping[dram0_data]
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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/**
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* This section holds data that should not be initialized at power up.
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* The section located in Internal SRAM memory region. The macro _NOINIT
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* can be used as attribute to place data into this section.
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* See the "esp_attr.h" file for more information.
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*/
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.noinit (NOLOAD):
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{
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. = ALIGN(4);
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_noinit_start = ABSOLUTE(.);
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*(.noinit .noinit.*)
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. = ALIGN(4) ;
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_noinit_end = ABSOLUTE(.);
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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2024-02-12 00:51:25 -05:00
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/* ldgen places all bss-related data to mapping[dram0_bss] (See esp_system/app.lf). */
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2022-12-06 00:46:03 -05:00
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mapping[dram0_bss]
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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2024-02-12 00:51:25 -05:00
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} > sram_seg
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2022-12-06 00:46:03 -05:00
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.flash.text :
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{
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_stext = .;
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_instruction_reserved_start = ABSOLUTE(.);
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_text_start = ABSOLUTE(.);
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mapping[flash_text]
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/** CPU will try to prefetch up to 16 bytes of
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* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += _esp_flash_mmap_prefetch_pad_size;
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_text_end = ABSOLUTE(.);
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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/**
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* Similar to _iram_start, this symbol goes here so it is
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* resolved by addr2line in preference to the first symbol in
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* the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} > default_code_seg
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/**
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* This dummy section represents the .flash.text section but in default_rodata_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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.flash_rodata_dummy (NOLOAD):
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{
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_flash_rodata_dummy_start = .;
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/* Start at the same alignment constraint than .flash.text */
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. = ALIGN(ALIGNOF(.flash.text));
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/* Create an empty gap as big as .flash.text section */
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. = . + SIZEOF(.flash.text);
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/* Prepare the alignment of the section above. Few bytes (0x20) must be
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* added for the mapping header. */
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2023-01-30 05:03:41 -05:00
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. = ALIGN(_esp_mmu_block_size) + 0x20;
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2022-12-06 00:46:03 -05:00
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_rodata_reserved_start = .;
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} > default_rodata_seg
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.flash.appdesc : ALIGN(0x10)
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
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*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
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/* Create an empty gap within this section. Thanks to this, the end of this
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* section will match .flash.rodata's begin address. Thus, both sections
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* will be merged when creating the final bin image. */
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. = ALIGN(ALIGNOF(.flash.rodata));
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2024-02-12 00:51:25 -05:00
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata)
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2022-12-06 00:46:03 -05:00
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.flash.rodata : ALIGN(0x10)
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{
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_flash_rodata_start = ABSOLUTE(.);
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mapping[flash_rodata]
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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. = (. + 7) & ~ 3;
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/*
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* C++ constructor and destructor tables
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* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
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*
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* RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
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* But the init_priority sections will be sorted for iteration in ascending order during startup.
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* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
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* Hence a different section is generated for the init_priority functions which is iterated in
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* ascending order during startup. The corresponding code can be found in startup.c.
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*/
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__init_priority_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
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__init_priority_array_end = ABSOLUTE(.);
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__init_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
|
|
|
|
__init_array_end = ABSOLUTE(.);
|
|
|
|
KEEP (*crtbegin.*(.dtors))
|
|
|
|
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
|
|
|
|
KEEP (*(SORT(.dtors.*)))
|
|
|
|
KEEP (*(.dtors))
|
|
|
|
/* C++ exception handlers table: */
|
|
|
|
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
|
|
|
*(.xt_except_desc)
|
|
|
|
*(.gnu.linkonce.h.*)
|
|
|
|
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
|
|
|
*(.xt_except_desc_end)
|
|
|
|
*(.dynamic)
|
|
|
|
*(.gnu.version_d)
|
|
|
|
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
|
|
|
|
soc_reserved_memory_region_start = ABSOLUTE(.);
|
|
|
|
KEEP (*(.reserved_memory_address))
|
|
|
|
soc_reserved_memory_region_end = ABSOLUTE(.);
|
|
|
|
_esp_system_init_fn_array_start = ABSOLUTE(.);
|
|
|
|
KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*)))
|
|
|
|
_esp_system_init_fn_array_end = ABSOLUTE(.);
|
|
|
|
_rodata_end = ABSOLUTE(.);
|
|
|
|
/* Literals are also RO data. */
|
|
|
|
_lit4_start = ABSOLUTE(.);
|
|
|
|
*(*.lit4)
|
|
|
|
*(.lit4.*)
|
|
|
|
*(.gnu.linkonce.lit4.*)
|
|
|
|
_lit4_end = ABSOLUTE(.);
|
2024-02-12 00:51:25 -05:00
|
|
|
. = ALIGN(ALIGNOF(.flash.tls));
|
|
|
|
} > default_rodata_seg
|
|
|
|
ASSERT_SECTIONS_GAP(.flash.rodata, .flash.tls)
|
|
|
|
|
|
|
|
.flash.tls : ALIGN(8)
|
|
|
|
{
|
2022-12-06 00:46:03 -05:00
|
|
|
_thread_local_start = ABSOLUTE(.);
|
|
|
|
*(.tdata)
|
|
|
|
*(.tdata.*)
|
|
|
|
*(.tbss)
|
|
|
|
*(.tbss.*)
|
|
|
|
_thread_local_end = ABSOLUTE(.);
|
|
|
|
_rodata_reserved_end = ABSOLUTE(.);
|
|
|
|
. = ALIGN(ALIGNOF(.eh_frame));
|
|
|
|
} > default_rodata_seg
|
2024-02-12 00:51:25 -05:00
|
|
|
ASSERT_SECTIONS_GAP(.flash.tls, .eh_frame)
|
2022-12-06 00:46:03 -05:00
|
|
|
|
|
|
|
/* Keep this section shall be at least aligned on 4 */
|
|
|
|
.eh_frame : ALIGN(8)
|
|
|
|
{
|
|
|
|
__eh_frame = ABSOLUTE(.);
|
|
|
|
KEEP (*(.eh_frame))
|
|
|
|
__eh_frame_end = ABSOLUTE(.);
|
|
|
|
/* Guarantee that this section and the next one will be merged by making
|
|
|
|
* them adjacent. */
|
|
|
|
. = ALIGN(ALIGNOF(.eh_frame_hdr));
|
|
|
|
} > default_rodata_seg
|
2024-02-12 00:51:25 -05:00
|
|
|
ASSERT_SECTIONS_GAP(.eh_frame, .eh_frame_hdr)
|
2022-12-06 00:46:03 -05:00
|
|
|
|
|
|
|
/* To avoid any exception in C++ exception frame unwinding code, this section
|
|
|
|
* shall be aligned on 8. */
|
|
|
|
.eh_frame_hdr : ALIGN(8)
|
|
|
|
{
|
|
|
|
__eh_frame_hdr = ABSOLUTE(.);
|
|
|
|
KEEP (*(.eh_frame_hdr))
|
|
|
|
__eh_frame_hdr_end = ABSOLUTE(.);
|
|
|
|
} > default_rodata_seg
|
|
|
|
|
|
|
|
.flash.rodata_noload (NOLOAD) :
|
|
|
|
{
|
|
|
|
. = ALIGN (4);
|
|
|
|
mapping[rodata_noload]
|
|
|
|
} > default_rodata_seg
|
|
|
|
|
|
|
|
/* Marks the end of data, bss and possibly rodata */
|
|
|
|
.dram0.heap_start (NOLOAD) :
|
|
|
|
{
|
|
|
|
. = ALIGN (16);
|
|
|
|
_heap_start = ABSOLUTE(.);
|
2024-02-12 00:51:25 -05:00
|
|
|
} > sram_seg
|
2022-12-06 00:46:03 -05:00
|
|
|
}
|