2022-06-07 03:01:05 -04:00
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/*
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Note: This is a compatibility header. Call the interfaces in esp_cpu.h instead
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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#include "esp_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) __attribute__((pure)) uint32_t cpu_ll_get_core_id(void)
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2022-06-07 03:01:05 -04:00
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{
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return esp_cpu_get_core_id();
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) uint32_t cpu_ll_get_cycle_count(void)
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2022-06-07 03:01:05 -04:00
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{
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2022-07-21 07:24:42 -04:00
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return (uint32_t)esp_cpu_get_cycle_count();
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2022-06-07 03:01:05 -04:00
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_set_cycle_count(uint32_t val)
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2022-06-07 03:01:05 -04:00
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{
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2022-07-19 01:20:07 -04:00
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esp_cpu_set_cycle_count((esp_cpu_cycle_count_t)val);
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2022-06-07 03:01:05 -04:00
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void *cpu_ll_get_sp(void)
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2022-06-07 03:01:05 -04:00
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{
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return esp_cpu_get_sp();
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_init_hwloop(void)
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2022-06-07 03:01:05 -04:00
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{
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; // Nothing to do. Contents moved to bootloader directly
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}
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#if SOC_CPU_BREAKPOINTS_NUM > 0
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_set_breakpoint(int id, uint32_t pc)
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2022-06-07 03:01:05 -04:00
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{
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esp_cpu_set_breakpoint(id, (const void *)pc);
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_clear_breakpoint(int id)
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2022-06-07 03:01:05 -04:00
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{
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esp_cpu_clear_breakpoint(id);
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}
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#endif // SOC_CPU_BREAKPOINTS_NUM > 0
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) __attribute__((pure)) uint32_t cpu_ll_ptr_to_pc(const void *addr)
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{
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return ((uint32_t) addr);
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) __attribute__((pure)) void *cpu_ll_pc_to_ptr(uint32_t pc)
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2022-06-07 03:01:05 -04:00
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{
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return esp_cpu_pc_to_addr(pc);
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated))
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void cpu_ll_set_watchpoint(int id, const void *addr, size_t size, bool on_read, bool on_write)
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{
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esp_cpu_watchpoint_trigger_t trigger;
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if (on_read && on_write) {
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trigger = ESP_CPU_WATCHPOINT_ACCESS;
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} else if (on_read) {
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trigger = ESP_CPU_WATCHPOINT_LOAD;
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} else {
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trigger = ESP_CPU_WATCHPOINT_STORE;
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}
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esp_cpu_set_watchpoint(id, addr, size, trigger);
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_clear_watchpoint(int id)
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2022-06-07 03:01:05 -04:00
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{
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esp_cpu_clear_watchpoint(id);
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) bool cpu_ll_is_debugger_attached(void)
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2022-06-07 03:01:05 -04:00
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{
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return esp_cpu_dbgr_is_attached();
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_break(void)
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2022-06-07 03:01:05 -04:00
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{
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esp_cpu_dbgr_break();
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_set_vecbase(const void *base)
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{
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esp_cpu_intr_set_ivt_addr(base);
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated)) void cpu_ll_waiti(void)
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2022-06-07 03:01:05 -04:00
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{
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esp_cpu_wait_for_intr();
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}
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2022-07-21 07:24:42 -04:00
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FORCE_INLINE_ATTR __attribute__((deprecated))
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void cpu_ll_compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
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2022-06-07 03:01:05 -04:00
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{
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#ifdef __clang_analyzer__
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//Teach clang-tidy that "addr" and "set" cannot be const as they can both be updated by S32C1I instruction
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volatile uint32_t temp;
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temp = *addr;
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*addr = temp;
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temp = *set;
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*set = temp;
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#endif
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#ifdef __XTENSA__
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#if XCHAL_HAVE_S32C1I
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__asm__ __volatile__ (
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"WSR %2, SCOMPARE1 \n"
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"S32C1I %0, %1, 0 \n"
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:"=r"(*set)
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:"r"(addr), "r"(compare), "0"(*set)
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);
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#else // XCHAL_HAVE_S32C1I
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uint32_t old_value;
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// No S32C1I, so do this by disabling and re-enabling interrupts (slower)
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uint32_t intlevel;
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__asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n"
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: "=r"(intlevel));
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old_value = *addr;
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if (old_value == compare) {
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*addr = *set;
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}
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__asm__ __volatile__ ("memw \n"
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"wsr %0, ps\n"
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:: "r"(intlevel));
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*set = old_value;
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#endif // XCHAL_HAVE_S32C1I
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#else
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uint32_t old_value;
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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old_value = *addr;
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if (old_value == compare) {
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*addr = *set;
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}
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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*set = old_value;
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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