2021-06-03 07:40:09 -04:00
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/*
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2022-03-15 06:25:05 -04:00
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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2021-06-03 07:40:09 -04:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2018-10-16 07:06:41 -04:00
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#include "esp_heap_caps.h"
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#include "unity.h"
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#include "esp_log.h"
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2022-05-17 22:45:06 -04:00
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#include "esp_private/spi_common_internal.h"
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2018-12-05 07:22:25 -05:00
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#include "sdkconfig.h"
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2018-10-16 07:06:41 -04:00
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2021-03-19 03:54:30 -04:00
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#if CONFIG_IDF_TARGET_ESP32
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2018-10-16 07:06:41 -04:00
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static const char TAG[] = "test_psram";
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2019-06-05 00:34:19 -04:00
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#ifdef CONFIG_SPIRAM
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2019-07-16 05:33:30 -04:00
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static void test_psram_content(void)
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2018-10-16 07:06:41 -04:00
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{
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const int test_size = 2048;
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uint32_t *test_area = heap_caps_malloc(test_size, MALLOC_CAP_SPIRAM);
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size_t p;
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size_t s=test_size;
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int errct=0;
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int initial_err=-1;
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for (p=0; p<(s/sizeof(int)); p+=4) {
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test_area[p]=p^0xAAAAAAAA;
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}
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for (p=0; p<(s/sizeof(int)); p+=4) {
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if (test_area[p]!=(p^0xAAAAAAAA)) {
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errct++;
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if (errct==1) initial_err=p*4;
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}
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}
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if (errct) {
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ESP_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %p\n", errct, s/32, initial_err+test_area);
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TEST_FAIL();
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} else {
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ESP_LOGI(TAG, "SPI SRAM memory test OK");
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}
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free(test_area);
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}
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2018-12-05 07:22:25 -05:00
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#endif
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2018-10-16 07:06:41 -04:00
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2019-10-31 00:00:46 -04:00
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bool psram_is_32mbit_ver0(void);
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2018-10-16 07:06:41 -04:00
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2019-10-31 00:00:46 -04:00
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static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host)
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{
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2018-10-16 07:06:41 -04:00
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bool claim_hspi = spicommon_periph_claim(HSPI_HOST, "ut-hspi");
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if (claim_hspi) ESP_LOGI(TAG, "HSPI claimed.");
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bool claim_vspi = spicommon_periph_claim(VSPI_HOST, "ut-vspi");
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if (claim_vspi) ESP_LOGI(TAG, "VSPI claimed.");
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2019-10-31 00:00:46 -04:00
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if (expected_occupied_host == HSPI_HOST) {
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TEST_ASSERT_FALSE(claim_hspi);
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TEST_ASSERT(claim_vspi);
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} else if (expected_occupied_host == VSPI_HOST) {
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TEST_ASSERT_FALSE(claim_vspi);
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TEST_ASSERT(claim_hspi);
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2018-10-16 07:06:41 -04:00
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} else {
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2019-10-31 00:00:46 -04:00
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TEST_ASSERT(claim_hspi);
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TEST_ASSERT(claim_vspi);
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2018-10-16 07:06:41 -04:00
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}
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2019-06-05 00:34:19 -04:00
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#ifdef CONFIG_SPIRAM
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2018-10-16 07:06:41 -04:00
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test_psram_content();
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#endif
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}
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2019-10-31 00:00:46 -04:00
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#if CONFIG_SPIRAM_OCCUPY_HSPI_HOST || CONFIG_SPIRAM_OCCUPY_VSPI_HOST
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2022-10-25 04:20:44 -04:00
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TEST_CASE("some spi bus occpied by psram", "[psram_4m]")
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2019-10-31 00:00:46 -04:00
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{
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2022-03-15 06:25:05 -04:00
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// NOTE: this unit test rely on the config that PSRAM of 8MB is used only when CONFIG_SPIRAM_BANKSWITCH_ENABLE is set
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2019-10-31 00:00:46 -04:00
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//currently all 8M psram don't need more SPI peripherals
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#if !CONFIG_SPIRAM || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
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#error unexpected test config, only psram 32MBit ver 0 at 80MHz will trigger the workaround
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#endif
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spi_host_device_t host;
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if (!psram_is_32mbit_ver0()) {
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TEST_FAIL_MESSAGE("unexpected psram version");
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}
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#if CONFIG_SPIRAM_OCCUPY_HSPI_HOST
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host = HSPI_HOST;
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#elif CONFIG_SPIRAM_OCCUPY_VSPI_HOST
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host = VSPI_HOST;
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#endif
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test_spi_bus_occupy(host);
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}
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#else
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TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
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{
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#if CONFIG_SPIRAM && CONFIG_SPIRAM_SPEED_80M
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#error unexpected test config, some runners using the UT_T1_PSRAMV0 but still perform this test.\
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they will not pass this test at 80MHz.
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#endif
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test_spi_bus_occupy(-1);
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}
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#endif
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2021-03-19 03:54:30 -04:00
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#endif // CONFIG_IDF_TARGET_ESP32
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