2022-01-05 03:14:03 -05:00
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/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DR_REG_UART_BASE 0x60000000
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#define DR_REG_SPI1_BASE 0x60002000
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#define DR_REG_SPI0_BASE 0x60003000
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#define DR_REG_GPIO_BASE 0x60004000
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#define DR_REG_GPIO_SD_BASE 0x60004f00
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#define DR_REG_FE2_BASE 0x60005000
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#define DR_REG_FE_BASE 0x60006000
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#define DR_REG_EFUSE_BASE 0x60007000
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#define DR_REG_RTCCNTL_BASE 0x60008000
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#define DR_REG_RTCIO_BASE 0x60008400
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#define DR_REG_SENS_BASE 0x60008800
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#define DR_REG_RTC_I2C_BASE 0x60008C00
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#define DR_REG_IO_MUX_BASE 0x60009000
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#define DR_REG_HINF_BASE 0x6000B000
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#define DR_REG_UHCI1_BASE 0x6000C000
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#define DR_REG_I2S_BASE 0x6000F000
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#define DR_REG_UART1_BASE 0x60010000
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#define DR_REG_BT_BASE 0x60011000
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#define DR_REG_I2C_EXT_BASE 0x60013000
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#define DR_REG_UHCI0_BASE 0x60014000
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#define DR_REG_SLCHOST_BASE 0x60015000
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#define DR_REG_RMT_BASE 0x60016000
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#define DR_REG_PCNT_BASE 0x60017000
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#define DR_REG_SLC_BASE 0x60018000
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#define DR_REG_LEDC_BASE 0x60019000
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#define DR_REG_NRX_BASE 0x6001CC00
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#define DR_REG_BB_BASE 0x6001D000
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#define DR_REG_PWM0_BASE 0x6001E000
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#define DR_REG_TIMERGROUP0_BASE 0x6001F000
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#define DR_REG_TIMERGROUP1_BASE 0x60020000
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#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
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#define DR_REG_SYSTIMER_BASE 0x60023000
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#define DR_REG_SPI2_BASE 0x60024000
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#define DR_REG_SPI3_BASE 0x60025000
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#define DR_REG_SYSCON_BASE 0x60026000
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#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
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#define DR_REG_I2C1_EXT_BASE 0x60027000
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#define DR_REG_SDMMC_BASE 0x60028000
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#define DR_REG_PERI_BACKUP_BASE 0x6002A000
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#define DR_REG_TWAI_BASE 0x6002B000
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#define DR_REG_PWM1_BASE 0x6002C000
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#define DR_REG_I2S1_BASE 0x6002D000
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#define DR_REG_UART2_BASE 0x6002E000
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2021-12-30 07:31:38 -05:00
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#define DR_REG_USB_SERIAL_JTAG_BASE 0x60038000
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2022-01-05 03:14:03 -05:00
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#define DR_REG_USB_WRAP_BASE 0x60039000
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#define DR_REG_AES_BASE 0x6003A000
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#define DR_REG_SHA_BASE 0x6003B000
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#define DR_REG_RSA_BASE 0x6003C000
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#define DR_REG_HMAC_BASE 0x6003E000
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#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000
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#define DR_REG_GDMA_BASE 0x6003F000
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#define DR_REG_APB_SARADC_BASE 0x60040000
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#define DR_REG_LCD_CAM_BASE 0x60041000
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#define DR_REG_SYSTEM_BASE 0x600C0000
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#define DR_REG_SENSITIVE_BASE 0x600C1000
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#define DR_REG_INTERRUPT_BASE 0x600C2000
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#define DR_REG_EXTMEM_BASE 0x600C4000
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#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000
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#define DR_REG_WORLD_CNTL_BASE 0x600D0000
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