esp-idf/components/idf_test/include/esp32s3/idf_performance_target.h

/*
 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#pragma once

#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC                            43

// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC                             90
// esp_sha() time to process 32KB of input data from RAM
#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB                                      1000
#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB                                    900

#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP                               18000
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              490000
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP                               45000
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP                              1300000
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP                               80000
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              2500000

#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                               15
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA                        15
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                            32
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA                     30

// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV                                      70
#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT                                     140
crypto: allocate all DMA descriptors to DMA capable memory. These were previously placed on the stack, but the stack could be placed in RTC RAM which is not DMA capable. 2021-11-17 04:43:22 -05:00			`/*`
spi: support spi on 8684 2022-01-11 22:30:29 -05:00			`* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD`
crypto: allocate all DMA descriptors to DMA capable memory. These were previously placed on the stack, but the stack could be placed in RTC RAM which is not DMA capable. 2021-11-17 04:43:22 -05:00			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`
mbedtls: merge changes from C3 2020-12-22 06:37:59 -05:00
bringup esp32-s3 on FPGA 2020-07-29 01:13:51 -04:00			`#pragma once`

AES/SHA: use GDMA driver instead of LL 2021-01-14 02:25:06 -05:00			`#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 43`
bringup esp32-s3 on FPGA 2020-07-29 01:13:51 -04:00
			`// SHA256 hardware throughput at 240MHz, threshold set lower than worst case`
crypto: allocate all DMA descriptors to DMA capable memory. These were previously placed on the stack, but the stack could be placed in RTC RAM which is not DMA capable. 2021-11-17 04:43:22 -05:00			`#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90`
bringup esp32-s3 on FPGA 2020-07-29 01:13:51 -04:00			`// esp_sha() time to process 32KB of input data from RAM`
			`#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 1000`
			`#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900`

crypto accelerator support on esp32s3 SHA: passing unit tests RSA: pass tests AES: tests passing 2020-08-19 02:39:12 -04:00			`#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 18000`
test_rsa.c: remove 'use_blinding' variable. The "mbedtls_rsa_private" has made f_rng function mandatory for the operation. Also updated the MAX_PERFORMANCE values with offset added with blinding Added the SOC_CCOMP_TIMER_SUPPORTED Check 2022-04-18 23:35:42 -04:00			`#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 490000`
mbedtls: merge changes from C3 2020-12-22 06:37:59 -05:00			`#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000`
test_rsa.c: remove 'use_blinding' variable. The "mbedtls_rsa_private" has made f_rng function mandatory for the operation. Also updated the MAX_PERFORMANCE values with offset added with blinding Added the SOC_CCOMP_TIMER_SUPPORTED Check 2022-04-18 23:35:42 -04:00			`#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 1300000`
crypto accelerator support on esp32s3 SHA: passing unit tests RSA: pass tests AES: tests passing 2020-08-19 02:39:12 -04:00			`#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000`
test_rsa.c: remove 'use_blinding' variable. The "mbedtls_rsa_private" has made f_rng function mandatory for the operation. Also updated the MAX_PERFORMANCE values with offset added with blinding Added the SOC_CCOMP_TIMER_SUPPORTED Check 2022-04-18 23:35:42 -04:00			`#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 2500000`
bringup esp32-s3 on FPGA 2020-07-29 01:13:51 -04:00
spi: support spi on 8684 2022-01-11 22:30:29 -05:00			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15`
			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15`
bringup esp32-s3 on FPGA 2020-07-29 01:13:51 -04:00			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32`
			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30`
unit_test: support reference clock, test delay function 2020-08-12 23:56:52 -04:00
			`// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)`
			`#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70`
			`#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140`