mirror of
https://github.com/nopnop2002/esp-idf-ssd1306.git
synced 2024-09-19 09:45:59 -04:00
316 lines
10 KiB
C
316 lines
10 KiB
C
#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/spi_master.h"
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#include "driver/gpio.h"
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#include "esp_log.h"
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#include "ssd1306.h"
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#define TAG "SSD1306"
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#if CONFIG_SPI2_HOST
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#define HOST_ID SPI2_HOST
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#elif CONFIG_SPI3_HOST
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#define HOST_ID SPI3_HOST
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#else
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#define HOST_ID SPI2_HOST // If i2c is selected
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#endif
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#define SPI_COMMAND_MODE 0
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#define SPI_DATA_MODE 1
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#define SPI_DEFAULT_FREQUENCY 1000000; // 1MHz
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int clock_speed_hz = SPI_DEFAULT_FREQUENCY;
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void spi_clock_speed(int speed) {
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ESP_LOGI(TAG, "SPI clock speed=%d MHz", speed/1000000);
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clock_speed_hz = speed;
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}
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void spi_master_init(SSD1306_t * dev, int16_t mosi, int16_t sclk, int16_t cs, int16_t dc, int16_t reset)
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{
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esp_err_t ret;
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gpio_reset_pin( cs );
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gpio_set_direction( cs, GPIO_MODE_OUTPUT );
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gpio_set_level( cs, 0 );
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gpio_reset_pin( dc );
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gpio_set_direction( dc, GPIO_MODE_OUTPUT );
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gpio_set_level( dc, 0 );
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if ( reset >= 0 ) {
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gpio_reset_pin( reset );
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gpio_set_direction( reset, GPIO_MODE_OUTPUT );
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gpio_set_level( reset, 0 );
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vTaskDelay( pdMS_TO_TICKS( 100 ) );
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gpio_set_level( reset, 1 );
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}
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spi_bus_config_t spi_bus_config = {
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.mosi_io_num = mosi,
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.miso_io_num = -1,
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.sclk_io_num = sclk,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1,
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.max_transfer_sz = 0,
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.flags = 0
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};
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ESP_LOGI(TAG, "SPI HOST_ID=%d", HOST_ID);
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ret = spi_bus_initialize( HOST_ID, &spi_bus_config, SPI_DMA_CH_AUTO );
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ESP_LOGI(TAG, "spi_bus_initialize=%d",ret);
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assert(ret==ESP_OK);
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spi_device_interface_config_t devcfg;
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memset( &devcfg, 0, sizeof( spi_device_interface_config_t ) );
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//devcfg.clock_speed_hz = SPI_DEFAULT_FREQUENCY;
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devcfg.clock_speed_hz = clock_speed_hz;
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devcfg.spics_io_num = cs;
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devcfg.queue_size = 1;
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spi_device_handle_t spi_device_handle;
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ret = spi_bus_add_device( HOST_ID, &devcfg, &spi_device_handle);
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ESP_LOGI(TAG, "spi_bus_add_device=%d",ret);
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assert(ret==ESP_OK);
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dev->_dc = dc;
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dev->_address = SPI_ADDRESS;
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dev->_flip = false;
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dev->_spi_device_handle = spi_device_handle;
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}
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void spi_device_add(SSD1306_t * dev, int16_t cs, int16_t dc, int16_t reset)
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{
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ESP_LOGW(TAG, "Will not install spi master driver");
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esp_err_t ret;
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gpio_reset_pin( cs );
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gpio_set_direction( cs, GPIO_MODE_OUTPUT );
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gpio_set_level( cs, 0 );
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gpio_reset_pin( dc );
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gpio_set_direction( dc, GPIO_MODE_OUTPUT );
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gpio_set_level( dc, 0 );
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if ( reset >= 0 ) {
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gpio_reset_pin( reset );
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gpio_set_direction( reset, GPIO_MODE_OUTPUT );
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gpio_set_level( reset, 0 );
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vTaskDelay( pdMS_TO_TICKS( 100 ) );
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gpio_set_level( reset, 1 );
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}
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#if 0
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spi_bus_config_t spi_bus_config = {
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.mosi_io_num = mosi,
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.miso_io_num = -1,
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.sclk_io_num = sclk,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1,
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.max_transfer_sz = 0,
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.flags = 0
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};
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ESP_LOGI(TAG, "SPI HOST_ID=%d", HOST_ID);
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ret = spi_bus_initialize( HOST_ID, &spi_bus_config, SPI_DMA_CH_AUTO );
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ESP_LOGI(TAG, "spi_bus_initialize=%d",ret);
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assert(ret==ESP_OK);
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#endif
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spi_device_interface_config_t devcfg;
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memset( &devcfg, 0, sizeof( spi_device_interface_config_t ) );
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//devcfg.clock_speed_hz = SPI_DEFAULT_FREQUENCY;
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devcfg.clock_speed_hz = clock_speed_hz;
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devcfg.spics_io_num = cs;
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devcfg.queue_size = 1;
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spi_device_handle_t spi_device_handle;
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ret = spi_bus_add_device( HOST_ID, &devcfg, &spi_device_handle);
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ESP_LOGI(TAG, "spi_bus_add_device=%d",ret);
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assert(ret==ESP_OK);
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dev->_dc = dc;
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dev->_address = SPI_ADDRESS;
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dev->_flip = false;
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dev->_spi_device_handle = spi_device_handle;
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}
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bool spi_master_write_byte(spi_device_handle_t SPIHandle, const uint8_t* Data, size_t DataLength )
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{
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spi_transaction_t SPITransaction;
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if ( DataLength > 0 ) {
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memset( &SPITransaction, 0, sizeof( spi_transaction_t ) );
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SPITransaction.length = DataLength * 8;
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SPITransaction.tx_buffer = Data;
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spi_device_transmit( SPIHandle, &SPITransaction );
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}
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return true;
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}
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bool spi_master_write_command(SSD1306_t * dev, uint8_t Command )
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{
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static uint8_t CommandByte = 0;
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CommandByte = Command;
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gpio_set_level( dev->_dc, SPI_COMMAND_MODE );
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return spi_master_write_byte( dev->_spi_device_handle, &CommandByte, 1 );
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}
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bool spi_master_write_data(SSD1306_t * dev, const uint8_t* Data, size_t DataLength )
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{
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gpio_set_level( dev->_dc, SPI_DATA_MODE );
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return spi_master_write_byte( dev->_spi_device_handle, Data, DataLength );
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}
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void spi_init(SSD1306_t * dev, int width, int height)
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{
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dev->_width = width;
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dev->_height = height;
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dev->_pages = 8;
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if (dev->_height == 32) dev->_pages = 4;
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spi_master_write_command(dev, OLED_CMD_DISPLAY_OFF); // AE
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spi_master_write_command(dev, OLED_CMD_SET_MUX_RATIO); // A8
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if (dev->_height == 64) spi_master_write_command(dev, 0x3F);
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if (dev->_height == 32) spi_master_write_command(dev, 0x1F);
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spi_master_write_command(dev, OLED_CMD_SET_DISPLAY_OFFSET); // D3
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spi_master_write_command(dev, 0x00);
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spi_master_write_command(dev, OLED_CONTROL_BYTE_DATA_STREAM); // 40
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if (dev->_flip) {
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spi_master_write_command(dev, OLED_CMD_SET_SEGMENT_REMAP_0); // A0
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} else {
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spi_master_write_command(dev, OLED_CMD_SET_SEGMENT_REMAP_1); // A1
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}
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//spi_master_write_command(dev, OLED_CMD_SET_SEGMENT_REMAP); // A1
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spi_master_write_command(dev, OLED_CMD_SET_COM_SCAN_MODE); // C8
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spi_master_write_command(dev, OLED_CMD_SET_DISPLAY_CLK_DIV); // D5
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spi_master_write_command(dev, 0x80);
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spi_master_write_command(dev, OLED_CMD_SET_COM_PIN_MAP); // DA
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if (dev->_height == 64) spi_master_write_command(dev, 0x12);
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if (dev->_height == 32) spi_master_write_command(dev, 0x02);
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spi_master_write_command(dev, OLED_CMD_SET_CONTRAST); // 81
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spi_master_write_command(dev, 0xFF);
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spi_master_write_command(dev, OLED_CMD_DISPLAY_RAM); // A4
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spi_master_write_command(dev, OLED_CMD_SET_VCOMH_DESELCT); // DB
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spi_master_write_command(dev, 0x40);
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spi_master_write_command(dev, OLED_CMD_SET_MEMORY_ADDR_MODE); // 20
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//spi_master_write_command(dev, OLED_CMD_SET_HORI_ADDR_MODE); // 00
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spi_master_write_command(dev, OLED_CMD_SET_PAGE_ADDR_MODE); // 02
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// Set Lower Column Start Address for Page Addressing Mode
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spi_master_write_command(dev, 0x00);
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// Set Higher Column Start Address for Page Addressing Mode
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spi_master_write_command(dev, 0x10);
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spi_master_write_command(dev, OLED_CMD_SET_CHARGE_PUMP); // 8D
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spi_master_write_command(dev, 0x14);
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spi_master_write_command(dev, OLED_CMD_DEACTIVE_SCROLL); // 2E
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spi_master_write_command(dev, OLED_CMD_DISPLAY_NORMAL); // A6
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spi_master_write_command(dev, OLED_CMD_DISPLAY_ON); // AF
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}
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void spi_display_image(SSD1306_t * dev, int page, int seg, uint8_t * images, int width)
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{
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if (page >= dev->_pages) return;
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if (seg >= dev->_width) return;
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int _seg = seg + CONFIG_OFFSETX;
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uint8_t columLow = _seg & 0x0F;
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uint8_t columHigh = (_seg >> 4) & 0x0F;
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int _page = page;
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if (dev->_flip) {
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_page = (dev->_pages - page) - 1;
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}
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// Set Lower Column Start Address for Page Addressing Mode
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spi_master_write_command(dev, (0x00 + columLow));
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// Set Higher Column Start Address for Page Addressing Mode
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spi_master_write_command(dev, (0x10 + columHigh));
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// Set Page Start Address for Page Addressing Mode
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spi_master_write_command(dev, 0xB0 | _page);
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spi_master_write_data(dev, images, width);
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}
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void spi_contrast(SSD1306_t * dev, int contrast) {
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int _contrast = contrast;
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if (contrast < 0x0) _contrast = 0;
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if (contrast > 0xFF) _contrast = 0xFF;
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spi_master_write_command(dev, OLED_CMD_SET_CONTRAST); // 81
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spi_master_write_command(dev, _contrast);
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}
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void spi_hardware_scroll(SSD1306_t * dev, ssd1306_scroll_type_t scroll)
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{
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if (scroll == SCROLL_RIGHT) {
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spi_master_write_command(dev, OLED_CMD_HORIZONTAL_RIGHT); // 26
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spi_master_write_command(dev, 0x00); // Dummy byte
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spi_master_write_command(dev, 0x00); // Define start page address
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spi_master_write_command(dev, 0x07); // Frame frequency
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spi_master_write_command(dev, 0x07); // Define end page address
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spi_master_write_command(dev, 0x00); //
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spi_master_write_command(dev, 0xFF); //
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spi_master_write_command(dev, OLED_CMD_ACTIVE_SCROLL); // 2F
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}
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if (scroll == SCROLL_LEFT) {
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spi_master_write_command(dev, OLED_CMD_HORIZONTAL_LEFT); // 27
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spi_master_write_command(dev, 0x00); // Dummy byte
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spi_master_write_command(dev, 0x00); // Define start page address
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spi_master_write_command(dev, 0x07); // Frame frequency
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spi_master_write_command(dev, 0x07); // Define end page address
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spi_master_write_command(dev, 0x00); //
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spi_master_write_command(dev, 0xFF); //
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spi_master_write_command(dev, OLED_CMD_ACTIVE_SCROLL); // 2F
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}
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if (scroll == SCROLL_DOWN) {
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spi_master_write_command(dev, OLED_CMD_CONTINUOUS_SCROLL); // 29
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spi_master_write_command(dev, 0x00); // Dummy byte
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spi_master_write_command(dev, 0x00); // Define start page address
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spi_master_write_command(dev, 0x07); // Frame frequency
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//spi_master_write_command(dev, 0x01); // Define end page address
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spi_master_write_command(dev, 0x00); // Define end page address
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spi_master_write_command(dev, 0x3F); // Vertical scrolling offset
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spi_master_write_command(dev, OLED_CMD_VERTICAL); // A3
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spi_master_write_command(dev, 0x00);
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if (dev->_height == 64)
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spi_master_write_command(dev, 0x40);
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if (dev->_height == 32)
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spi_master_write_command(dev, 0x20);
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spi_master_write_command(dev, OLED_CMD_ACTIVE_SCROLL); // 2F
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}
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if (scroll == SCROLL_UP) {
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spi_master_write_command(dev, OLED_CMD_CONTINUOUS_SCROLL); // 29
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spi_master_write_command(dev, 0x00); // Dummy byte
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spi_master_write_command(dev, 0x00); // Define start page address
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spi_master_write_command(dev, 0x07); // Frame frequency
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//spi_master_write_command(dev, 0x01); // Define end page address
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spi_master_write_command(dev, 0x00); // Define end page address
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spi_master_write_command(dev, 0x01); // Vertical scrolling offset
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spi_master_write_command(dev, OLED_CMD_VERTICAL); // A3
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spi_master_write_command(dev, 0x00);
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if (dev->_height == 64)
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spi_master_write_command(dev, 0x40);
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if (dev->_height == 32)
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spi_master_write_command(dev, 0x20);
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spi_master_write_command(dev, OLED_CMD_ACTIVE_SCROLL); // 2F
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}
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if (scroll == SCROLL_STOP) {
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spi_master_write_command(dev, OLED_CMD_DEACTIVE_SCROLL); // 2E
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}
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}
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