mirror of
https://github.com/alexandrebobkov/ESP-Nodes.git
synced 2024-10-05 20:47:50 -04:00
.
This commit is contained in:
parent
26dadd559c
commit
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50
ESP32-Rainmaker-Switch/build/.ninja_log
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ESP32-Rainmaker-Switch/build/.ninja_log
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# Rule for linking C static library.
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rule C_STATIC_LIBRARY_LINKER____idf_qrcode_
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#############################################
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||||
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rule C_COMPILER____idf_app_wifi_
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description = Linking C static library $TARGET_FILE
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# Rule for compiling C files.
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||||
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||||
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|
||||
description = Building C object $out
|
||||
|
||||
|
||||
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||||
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||||
description = Linking C static library $TARGET_FILE
|
||||
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|
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|
||||
|
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|
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|
||||
|
||||
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|
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|
||||
description = Re-running CMake...
|
||||
generator = 1
|
||||
|
||||
|
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||||
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rule CLEAN
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||||
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||||
description = Cleaning all built files...
|
||||
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||||
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||||
#############################################
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# Rule for printing all primary targets available.
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|
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||||
21928
ESP32-Rainmaker-Switch/build/build.ninja
Normal file
21928
ESP32-Rainmaker-Switch/build/build.ninja
Normal file
File diff suppressed because one or more lines are too long
@ -1,3 +0,0 @@
|
||||
# CMAKE generated file: DO NOT EDIT!
|
||||
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|
||||
|
||||
139
ESP32-Rainmaker-Switch/build/esp-idf/esp_system/ld/memory.ld
Normal file
139
ESP32-Rainmaker-Switch/build/esp-idf/esp_system/ld/memory.ld
Normal file
@ -0,0 +1,139 @@
|
||||
/*
|
||||
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
|
||||
*
|
||||
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
*/
|
||||
/**
|
||||
|
||||
* ESP32-C3 Linker Script Memory Layout
|
||||
|
||||
* This file describes the memory layout (memory blocks) by virtual memory addresses.
|
||||
|
||||
* This linker script is passed through the C preprocessor to include configuration options.
|
||||
|
||||
* Please use preprocessor features sparingly!
|
||||
|
||||
* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
|
||||
|
||||
*/
|
||||
/*
|
||||
|
||||
* Automatically generated file. DO NOT EDIT.
|
||||
|
||||
* Espressif IoT Development Framework (ESP-IDF) 5.2.2 Configuration Header
|
||||
|
||||
*/
|
||||
|
||||
/* List of deprecated options */
|
||||
/*
|
||||
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
|
||||
*
|
||||
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
*/
|
||||
/* CPU instruction prefetch padding size for flash mmap scenario */
|
||||
_esp_flash_mmap_prefetch_pad_size = 16;
|
||||
/* CPU instruction prefetch padding size for memory protection scenario */
|
||||
_esp_memprot_prefetch_pad_size = 16;
|
||||
/* Memory alignment size for PMS */
|
||||
_esp_memprot_align_size = 512;
|
||||
_esp_mmu_block_size = (0x10000);
|
||||
/* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). For rtc_timer_data_in_rtc_mem section. */
|
||||
/**
|
||||
|
||||
* physical memory is mapped twice to the vritual address (IRAM and DRAM).
|
||||
|
||||
* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
|
||||
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
/**
|
||||
|
||||
* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
|
||||
|
||||
* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
|
||||
|
||||
* are connected to the data port of the CPU and eg allow byte-wise access.
|
||||
|
||||
*/
|
||||
/* IRAM for PRO CPU. */
|
||||
iram0_0_seg (RX) : org = (0x4037C000 + 0x4000), len = 0x403CE710 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
|
||||
/* Flash mapped instruction data */
|
||||
iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20
|
||||
/**
|
||||
|
||||
* (0x20 offset above is a convenience for the app binary image generation.
|
||||
|
||||
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
|
||||
|
||||
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
|
||||
|
||||
* header. Setting this offset makes it simple to meet the flash cache MMU's
|
||||
|
||||
* constraint that (paddr % 64KB == vaddr % 64KB).)
|
||||
|
||||
*/
|
||||
/**
|
||||
|
||||
* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
|
||||
|
||||
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
|
||||
|
||||
*/
|
||||
dram0_0_seg (RW) : org = (0x3FC7C000 + 0x4000), len = 0x403CE710 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
|
||||
/* Flash mapped constant data */
|
||||
drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
|
||||
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
|
||||
/**
|
||||
|
||||
* RTC fast memory (executable). Persists over deep sleep.
|
||||
|
||||
*/
|
||||
rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - (0 + (24))
|
||||
/* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value.
|
||||
|
||||
It reserves the amount of RTC fast memory that we use for this memory segment.
|
||||
|
||||
This segment is intended for keeping:
|
||||
|
||||
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
|
||||
|
||||
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
|
||||
|
||||
The aim of this is to keep data that will not be moved around and have a fixed address.
|
||||
|
||||
*/
|
||||
rtc_reserved_seg(RW) : org = 0x50000000 + 0x2000 - (0 + (24)), len = (0 + (24))
|
||||
}
|
||||
/* Heap ends at top of dram0_0_seg */
|
||||
_heap_end = 0x40000000;
|
||||
_data_seg_org = ORIGIN(rtc_data_seg);
|
||||
/**
|
||||
|
||||
* The lines below define location alias for .rtc.data section
|
||||
|
||||
* As C3 only has RTC fast memory, this is not configurable like on other targets
|
||||
|
||||
*/
|
||||
REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
|
||||
REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
|
||||
REGION_ALIAS("rtc_data_location", rtc_iram_seg );
|
||||
REGION_ALIAS("default_code_seg", iram0_2_seg);
|
||||
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
|
||||
/**
|
||||
|
||||
* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
|
||||
|
||||
* also be first in the segment.
|
||||
|
||||
*/
|
||||
ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
|
||||
".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
|
||||
@ -0,0 +1,437 @@
|
||||
/*
|
||||
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
|
||||
*
|
||||
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
*/
|
||||
/*
|
||||
|
||||
* Automatically generated file. DO NOT EDIT.
|
||||
|
||||
* Espressif IoT Development Framework (ESP-IDF) 5.2.2 Configuration Header
|
||||
|
||||
*/
|
||||
|
||||
/* List of deprecated options */
|
||||
/* Default entry point */
|
||||
ENTRY(call_start_cpu0);
|
||||
SECTIONS
|
||||
{
|
||||
/**
|
||||
|
||||
* RTC fast memory holds RTC wake stub code,
|
||||
|
||||
* including from any source file named rtc_wake_stub*.c
|
||||
|
||||
*/
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_fast_start = ABSOLUTE(.);
|
||||
mapping[rtc_text]
|
||||
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
|
||||
*(.rtc_text_end_test)
|
||||
/* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */
|
||||
. += _esp_memprot_prefetch_pad_size;
|
||||
. = ALIGN(4);
|
||||
_rtc_text_end = ABSOLUTE(.);
|
||||
} > rtc_iram_seg
|
||||
/**
|
||||
|
||||
* This section located in RTC FAST Memory area.
|
||||
|
||||
* It holds data marked with RTC_FAST_ATTR attribute.
|
||||
|
||||
* See the file "esp_attr.h" for more information.
|
||||
|
||||
*/
|
||||
.rtc.force_fast :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_fast_start = ABSOLUTE(.);
|
||||
mapping[rtc_force_fast]
|
||||
*(.rtc.force_fast .rtc.force_fast.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_fast_end = ABSOLUTE(.);
|
||||
} > rtc_data_seg
|
||||
/**
|
||||
|
||||
* RTC data section holds RTC wake stub
|
||||
|
||||
* data/rodata, including from any source file
|
||||
|
||||
* named rtc_wake_stub*.c and the data marked with
|
||||
|
||||
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
|
||||
|
||||
*/
|
||||
.rtc.data :
|
||||
{
|
||||
_rtc_data_start = ABSOLUTE(.);
|
||||
mapping[rtc_data]
|
||||
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
|
||||
_rtc_data_end = ABSOLUTE(.);
|
||||
} > rtc_data_location
|
||||
/* RTC bss, from any source file named rtc_wake_stub*.c */
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
|
||||
*rtc_wake_stub*.*(COMMON)
|
||||
mapping[rtc_bss]
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} > rtc_data_location
|
||||
/**
|
||||
|
||||
* This section holds data that should not be initialized at power up
|
||||
|
||||
* and will be retained during deep sleep.
|
||||
|
||||
* User data marked with RTC_NOINIT_ATTR will be placed
|
||||
|
||||
* into this section. See the file "esp_attr.h" for more information.
|
||||
|
||||
*/
|
||||
.rtc_noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_noinit_start = ABSOLUTE(.);
|
||||
*(.rtc_noinit .rtc_noinit.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_noinit_end = ABSOLUTE(.);
|
||||
} > rtc_data_location
|
||||
/**
|
||||
|
||||
* This section located in RTC SLOW Memory area.
|
||||
|
||||
* It holds data marked with RTC_SLOW_ATTR attribute.
|
||||
|
||||
* See the file "esp_attr.h" for more information.
|
||||
|
||||
*/
|
||||
.rtc.force_slow :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_slow_start = ABSOLUTE(.);
|
||||
*(.rtc.force_slow .rtc.force_slow.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_slow_end = ABSOLUTE(.);
|
||||
} > rtc_slow_seg
|
||||
/**
|
||||
|
||||
* This section holds RTC data that should have fixed addresses.
|
||||
|
||||
* The data are not initialized at power-up and are retained during deep sleep.
|
||||
|
||||
*/
|
||||
.rtc_reserved (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_reserved_start = ABSOLUTE(.);
|
||||
/* New data can only be added here to ensure existing data are not moved.
|
||||
|
||||
Because data have adhered to the end of the segment and code is relied on it.
|
||||
|
||||
>> put new data here << */
|
||||
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
|
||||
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
|
||||
_rtc_reserved_end = ABSOLUTE(.);
|
||||
} > rtc_reserved_seg
|
||||
_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
|
||||
ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
|
||||
"RTC reserved segment data does not fit.")
|
||||
/* Get size of rtc slow data based on rtc_data_location alias */
|
||||
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
|
||||
? (_rtc_force_slow_end - _rtc_data_start)
|
||||
: (_rtc_force_slow_end - _rtc_force_slow_start);
|
||||
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
|
||||
? (_rtc_force_fast_end - _rtc_fast_start)
|
||||
: (_rtc_noinit_end - _rtc_fast_start);
|
||||
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
|
||||
"RTC_SLOW segment data does not fit.")
|
||||
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
|
||||
"RTC_FAST segment data does not fit.")
|
||||
.iram0.text :
|
||||
{
|
||||
_iram_start = ABSOLUTE(.);
|
||||
/* Vectors go to start of IRAM */
|
||||
ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
|
||||
KEEP(*(.exception_vectors_table.text));
|
||||
KEEP(*(.exception_vectors.text));
|
||||
. = ALIGN(4);
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
mapping[iram0_text]
|
||||
} > iram0_0_seg
|
||||
/**
|
||||
|
||||
* This section is required to skip .iram0.text area because iram0_0_seg and
|
||||
|
||||
* dram0_0_seg reflect the same address space on different buses.
|
||||
|
||||
*/
|
||||
.dram0.dummy (NOLOAD):
|
||||
{
|
||||
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
|
||||
} > dram0_0_seg
|
||||
.dram0.data :
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
__global_pointer$ = . + 0x800;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.jcr)
|
||||
mapping[dram0_data]
|
||||
_data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} > dram0_0_seg
|
||||
/**
|
||||
|
||||
* This section holds data that should not be initialized at power up.
|
||||
|
||||
* The section located in Internal SRAM memory region. The macro _NOINIT
|
||||
|
||||
* can be used as attribute to place data into this section.
|
||||
|
||||
* See the "esp_attr.h" file for more information.
|
||||
|
||||
*/
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_noinit_start = ABSOLUTE(.);
|
||||
*(.noinit .noinit.*)
|
||||
. = ALIGN(4) ;
|
||||
_noinit_end = ABSOLUTE(.);
|
||||
} > dram0_0_seg
|
||||
/* Shared RAM */
|
||||
.dram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
mapping[dram0_bss]
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} > dram0_0_seg
|
||||
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
|
||||
.flash.text :
|
||||
{
|
||||
_stext = .;
|
||||
_instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
|
||||
_text_start = ABSOLUTE(.);
|
||||
mapping[flash_text]
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
/** CPU will try to prefetch up to 16 bytes of
|
||||
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
|
||||
* dummy bytes to ensure this
|
||||
|
||||
*/
|
||||
. += _esp_flash_mmap_prefetch_pad_size;
|
||||
_text_end = ABSOLUTE(.);
|
||||
_instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */
|
||||
_etext = .;
|
||||
/**
|
||||
|
||||
* Similar to _iram_start, this symbol goes here so it is
|
||||
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
|
||||
* the flash.text segment.
|
||||
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} > default_code_seg
|
||||
/**
|
||||
|
||||
* This dummy section represents the .flash.text section but in default_rodata_seg.
|
||||
|
||||
* Thus, it must have its alignment and (at least) its size.
|
||||
|
||||
*/
|
||||
.flash_rodata_dummy (NOLOAD):
|
||||
{
|
||||
_flash_rodata_dummy_start = .;
|
||||
/* Start at the same alignment constraint than .flash.text */
|
||||
. = ALIGN(ALIGNOF(.flash.text));
|
||||
/* Create an empty gap as big as .flash.text section */
|
||||
. = . + SIZEOF(.flash.text);
|
||||
/* Prepare the alignment of the section above. Few bytes (0x20) must be
|
||||
|
||||
* added for the mapping header. */
|
||||
. = ALIGN(_esp_mmu_block_size) + 0x20;
|
||||
} > default_rodata_seg
|
||||
.flash.appdesc : ALIGN(0x10)
|
||||
{
|
||||
_rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
/* Create an empty gap within this section. Thanks to this, the end of this
|
||||
|
||||
* section will match .flash.rodata's begin address. Thus, both sections
|
||||
|
||||
* will be merged when creating the final bin image. */
|
||||
. = ALIGN(ALIGNOF(.flash.rodata));
|
||||
} >default_rodata_seg
|
||||
.flash.rodata : ALIGN(0x10)
|
||||
{
|
||||
_flash_rodata_start = ABSOLUTE(.);
|
||||
mapping[flash_rodata]
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 7) & ~ 3;
|
||||
/*
|
||||
|
||||
* C++ constructor and destructor tables
|
||||
|
||||
* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
|
||||
|
||||
*
|
||||
|
||||
* RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
|
||||
|
||||
* But the init_priority sections will be sorted for iteration in ascending order during startup.
|
||||
|
||||
* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
|
||||
|
||||
* Hence a different section is generated for the init_priority functions which is iterated in
|
||||
|
||||
* ascending order during startup. The corresponding code can be found in startup.c.
|
||||
|
||||
*/
|
||||
__init_priority_array_start = ABSOLUTE(.);
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
|
||||
__init_priority_array_end = ABSOLUTE(.);
|
||||
__init_array_start = ABSOLUTE(.);
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
|
||||
__init_array_end = ABSOLUTE(.);
|
||||
KEEP (*crtbegin.*(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
|
||||
soc_reserved_memory_region_start = ABSOLUTE(.);
|
||||
KEEP (*(.reserved_memory_address))
|
||||
soc_reserved_memory_region_end = ABSOLUTE(.);
|
||||
/* System init functions registered via ESP_SYSTEM_INIT_FN */
|
||||
_esp_system_init_fn_array_start = ABSOLUTE(.);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
|
||||
_esp_system_init_fn_array_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
} > default_rodata_seg
|
||||
/*
|
||||
|
||||
This section is a place where we dump all the rodata which aren't used at runtime,
|
||||
|
||||
so as to avoid binary size increase
|
||||
|
||||
*/
|
||||
.flash.rodata_noload (NOLOAD) :
|
||||
{
|
||||
/*
|
||||
|
||||
This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address
|
||||
|
||||
We don't need to include the noload rodata in this section
|
||||
|
||||
*/
|
||||
_rodata_reserved_end = ABSOLUTE(.);
|
||||
. = ALIGN (4);
|
||||
mapping[rodata_noload]
|
||||
} > default_rodata_seg
|
||||
/* Marks the end of IRAM code segment */
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
/* iram_end_test section exists for use by Memprot unit tests only */
|
||||
*(.iram_end_test)
|
||||
/* ESP32-C3 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
|
||||
. += _esp_memprot_prefetch_pad_size;
|
||||
. = ALIGN(_esp_memprot_align_size);
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} > iram0_0_seg
|
||||
.iram0.data :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_iram_data_start = ABSOLUTE(.);
|
||||
mapping[iram0_data]
|
||||
_iram_data_end = ABSOLUTE(.);
|
||||
} > iram0_0_seg
|
||||
.iram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_iram_bss_start = ABSOLUTE(.);
|
||||
mapping[iram0_bss]
|
||||
_iram_bss_end = ABSOLUTE(.);
|
||||
. = ALIGN(16);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} > iram0_0_seg
|
||||
/* Marks the end of data, bss and possibly rodata */
|
||||
.dram0.heap_start (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_heap_start = ABSOLUTE(.);
|
||||
} > dram0_0_seg
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
}
|
||||
}
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
|
||||
"DRAM segment data does not fit.")
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
1
ESP32-Rainmaker-Switch/build/ota_data_initial.bin
Normal file
1
ESP32-Rainmaker-Switch/build/ota_data_initial.bin
Normal file
File diff suppressed because one or more lines are too long
BIN
ESP32-Rainmaker-Switch/build/partition_table/partition-table.bin
Normal file
BIN
ESP32-Rainmaker-Switch/build/partition_table/partition-table.bin
Normal file
Binary file not shown.
Loading…
Reference in New Issue
Block a user